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I suspect that the table of pseudo ops on the page RISC-V Assembler Referencejr offset is wrongly described and mapped.
It should take a register argument, so be jr rs1. And then map to jalr x0,rs1,0?
The text was updated successfully, but these errors were encountered:
Hi,
I suspect that the table of pseudo ops on the page RISC-V Assembler Reference
jr offset
is wrongly described and mapped.It should take a register argument, so be
jr rs1
. And then map tojalr x0,rs1,0
?The text was updated successfully, but these errors were encountered: