README.md

VerilogHDL-Codes

It includes Synthesizable Verilog Source Codes(DUT), Test-bench and simulation results.

-N Bit ALU

-Clock_Divide_by9

-Counter

-Counter+BCD

-Ripple_Counter_Encoder

-Asynchronous FIFO

-FSM_Mealy

-FSM_Mealy_Using_TASK_for_validation

-FSM_Mealy_Test_Automation_Using_perl

-FSM_Moore

-FSM_Moore_Using_TASK_for_validation

-FSM_Moore_Test_Automation_Using_perl