-
Notifications
You must be signed in to change notification settings - Fork 0
/
mouse_test.vhf
executable file
·304 lines (274 loc) · 10.5 KB
/
mouse_test.vhf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application : sch2hdl
-- / / Filename : mouse_test.vhf
-- /___/ /\ Timestamp : 05/09/2012 15:22:52
-- \ \ / \
-- \___\/\___\
--
--Command: sch2hdl -sympath F:/paint/ipcore_dir -intstyle ise -family spartan3e -flat -suppress -vhdl F:/paint/mouse_test.vhf -w F:/paint/mouse_test.sch
--Design Name: mouse_test
--Device: spartan3e
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesized and simulated, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity main_MUSER_mouse_test is
port ( clk : in std_logic;
rst : in std_logic;
btn_l : out std_logic;
btn_m : out std_logic;
btn_r : out std_logic;
data_ready : out std_logic;
x : out std_logic_vector (7 downto 0);
y : out std_logic_vector (7 downto 0);
ps2_clock : inout std_logic;
ps2_data : inout std_logic);
end main_MUSER_mouse_test;
architecture BEHAVIORAL of main_MUSER_mouse_test is
attribute IOSTANDARD : string ;
attribute SLEW : string ;
attribute DRIVE : string ;
attribute IBUF_DELAY_VALUE : string ;
attribute IFD_DELAY_VALUE : string ;
attribute BOX_TYPE : string ;
signal XLXN_7 : std_logic;
signal XLXN_8 : std_logic;
signal XLXN_32 : std_logic;
signal XLXN_34 : std_logic;
signal XLXN_35 : std_logic;
signal XLXN_36 : std_logic;
signal XLXN_38 : std_logic;
signal XLXN_49 : std_logic;
signal XLXN_52 : std_logic;
signal XLXN_53 : std_logic;
signal XLXN_56 : std_logic_vector (7 downto 0);
signal XLXN_57 : std_logic_vector (7 downto 0);
component ps2_rx
port ( clk : in std_logic;
reset : in std_logic;
ps2d : in std_logic;
ps2c : in std_logic;
rx_en : in std_logic;
rx_done : out std_logic;
dout : out std_logic_vector (7 downto 0));
end component;
component IOBUF
port ( I : in std_logic;
IO : inout std_logic;
O : out std_logic;
T : in std_logic);
end component;
attribute IOSTANDARD of IOBUF : component is "DEFAULT";
attribute SLEW of IOBUF : component is "SLOW";
attribute DRIVE of IOBUF : component is "12";
attribute IBUF_DELAY_VALUE of IOBUF : component is "0";
attribute IFD_DELAY_VALUE of IOBUF : component is "AUTO";
attribute BOX_TYPE of IOBUF : component is "BLACK_BOX";
component ps2_tx
port ( clk : in std_logic;
reset : in std_logic;
wr_ps2 : in std_logic;
ps2c_in : in std_logic;
din : in std_logic_vector (7 downto 0);
ps2c_out : out std_logic;
tx_idle : out std_logic;
tx_done : out std_logic;
ps2d_in : in std_logic;
ps2d_out : out std_logic);
end component;
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component driver
port ( clk : in std_logic;
reset : in std_logic;
tx_done : in std_logic;
rx_done : in std_logic;
rx_data : in std_logic_vector (7 downto 0);
wr : out std_logic;
ready : out std_logic;
btn_l : out std_logic;
btn_m : out std_logic;
btn_r : out std_logic;
x : out std_logic_vector (7 downto 0);
y : out std_logic_vector (7 downto 0);
tx_data : out std_logic_vector (7 downto 0));
end component;
begin
XLXI_1 : ps2_rx
port map (clk=>clk,
ps2c=>XLXN_8,
ps2d=>XLXN_7,
reset=>rst,
rx_en=>XLXN_34,
dout(7 downto 0)=>XLXN_56(7 downto 0),
rx_done=>XLXN_52);
XLXI_2 : IOBUF
port map (I=>XLXN_36,
T=>XLXN_38,
O=>XLXN_7,
IO=>ps2_data);
XLXI_7 : IOBUF
port map (I=>XLXN_35,
T=>XLXN_32,
O=>XLXN_8,
IO=>ps2_clock);
XLXI_12 : ps2_tx
port map (clk=>clk,
din(7 downto 0)=>XLXN_57(7 downto 0),
ps2c_in=>XLXN_8,
ps2d_in=>XLXN_7,
reset=>rst,
wr_ps2=>XLXN_49,
ps2c_out=>XLXN_32,
ps2d_out=>XLXN_38,
tx_done=>XLXN_53,
tx_idle=>XLXN_34);
XLXI_15 : GND
port map (G=>XLXN_35);
XLXI_16 : GND
port map (G=>XLXN_36);
XLXI_24 : driver
port map (clk=>clk,
reset=>rst,
rx_data(7 downto 0)=>XLXN_56(7 downto 0),
rx_done=>XLXN_52,
tx_done=>XLXN_53,
btn_l=>btn_l,
btn_m=>btn_m,
btn_r=>btn_r,
ready=>data_ready,
tx_data(7 downto 0)=>XLXN_57(7 downto 0),
wr=>XLXN_49,
x(7 downto 0)=>x(7 downto 0),
y(7 downto 0)=>y(7 downto 0));
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity mouse_test is
port ( clk : in std_logic;
rst : in std_logic;
vga_c : out std_logic_vector (2 downto 0);
vga_hs : out std_logic;
vga_vs : out std_logic;
ps2_clock : inout std_logic;
ps2_data : inout std_logic);
end mouse_test;
architecture BEHAVIORAL of mouse_test is
signal XLXN_34 : std_logic;
signal XLXN_35 : std_logic;
signal XLXN_36 : std_logic;
signal XLXN_37 : std_logic_vector (7 downto 0);
signal XLXN_38 : std_logic_vector (7 downto 0);
signal XLXN_47 : std_logic_vector (7 downto 0);
signal XLXN_48 : std_logic_vector (7 downto 0);
signal XLXN_54 : std_logic_vector (0 downto 0);
signal XLXN_55 : std_logic_vector (15 downto 0);
signal XLXN_56 : std_logic_vector (15 downto 0);
signal XLXN_57 : std_logic_vector (0 downto 0);
signal XLXN_58 : std_logic_vector (0 downto 0);
component main_MUSER_mouse_test
port ( clk : in std_logic;
rst : in std_logic;
ps2_data : inout std_logic;
ps2_clock : inout std_logic;
x : out std_logic_vector (7 downto 0);
y : out std_logic_vector (7 downto 0);
btn_r : out std_logic;
btn_m : out std_logic;
btn_l : out std_logic;
data_ready : out std_logic);
end component;
component controller
port ( clk : in std_logic;
rst : in std_logic;
btn_l : in std_logic;
btn_r : in std_logic;
mouse_rdy : in std_logic;
x_in : in std_logic_vector (7 downto 0);
y_in : in std_logic_vector (7 downto 0);
data : out std_logic;
wr : out std_logic;
x_out : out std_logic_vector (7 downto 0);
y_out : out std_logic_vector (7 downto 0);
addr : out std_logic_vector (15 downto 0));
end component;
component vga
port ( data : in std_logic;
clk : in std_logic;
rst : in std_logic;
x_in : in std_logic_vector (7 downto 0);
y_in : in std_logic_vector (7 downto 0);
vga_hs : out std_logic;
vga_vs : out std_logic;
vga_c : out std_logic_vector (2 downto 0);
addr : out std_logic_vector (15 downto 0));
end component;
component RAM
port ( addra : in std_logic_vector (15 downto 0);
dina : in std_logic_vector (0 downto 0);
wea : in std_logic_vector (0 downto 0);
clka : in std_logic;
addrb : in std_logic_vector (15 downto 0);
clkb : in std_logic;
doutb : out std_logic_vector (0 downto 0));
end component;
begin
XLXI_1 : main_MUSER_mouse_test
port map (clk=>clk,
rst=>rst,
btn_l=>XLXN_34,
btn_m=>open,
btn_r=>XLXN_35,
data_ready=>XLXN_36,
x(7 downto 0)=>XLXN_37(7 downto 0),
y(7 downto 0)=>XLXN_38(7 downto 0),
ps2_clock=>ps2_clock,
ps2_data=>ps2_data);
XLXI_12 : controller
port map (btn_l=>XLXN_34,
btn_r=>XLXN_35,
clk=>clk,
mouse_rdy=>XLXN_36,
rst=>rst,
x_in(7 downto 0)=>XLXN_37(7 downto 0),
y_in(7 downto 0)=>XLXN_38(7 downto 0),
addr(15 downto 0)=>XLXN_56(15 downto 0),
data=>XLXN_57(0),
wr=>XLXN_58(0),
x_out(7 downto 0)=>XLXN_47(7 downto 0),
y_out(7 downto 0)=>XLXN_48(7 downto 0));
XLXI_13 : vga
port map (clk=>clk,
data=>XLXN_54(0),
rst=>rst,
x_in(7 downto 0)=>XLXN_47(7 downto 0),
y_in(7 downto 0)=>XLXN_48(7 downto 0),
addr(15 downto 0)=>XLXN_55(15 downto 0),
vga_c(2 downto 0)=>vga_c(2 downto 0),
vga_hs=>vga_hs,
vga_vs=>vga_vs);
XLXI_14 : RAM
port map (addra(15 downto 0)=>XLXN_56(15 downto 0),
addrb(15 downto 0)=>XLXN_55(15 downto 0),
clka=>clk,
clkb=>clk,
dina(0)=>XLXN_57(0),
wea(0)=>XLXN_58(0),
doutb(0)=>XLXN_54(0));
end BEHAVIORAL;