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nios_0.v
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nios_0.v
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//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DM9000A_avalonS_arbitrator (
// inputs:
DM9000A_avalonS_irq,
DM9000A_avalonS_readdata,
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
reset_n,
// outputs:
DM9000A_avalonS_address,
DM9000A_avalonS_chipselect_n,
DM9000A_avalonS_irq_from_sa,
DM9000A_avalonS_read_n,
DM9000A_avalonS_readdata_from_sa,
DM9000A_avalonS_reset_n,
DM9000A_avalonS_wait_counter_eq_0,
DM9000A_avalonS_write_n,
DM9000A_avalonS_writedata,
cpu_0_data_master_granted_DM9000A_avalonS,
cpu_0_data_master_qualified_request_DM9000A_avalonS,
cpu_0_data_master_read_data_valid_DM9000A_avalonS,
cpu_0_data_master_requests_DM9000A_avalonS,
d1_DM9000A_avalonS_end_xfer
)
;
output DM9000A_avalonS_address;
output DM9000A_avalonS_chipselect_n;
output DM9000A_avalonS_irq_from_sa;
output DM9000A_avalonS_read_n;
output [ 15: 0] DM9000A_avalonS_readdata_from_sa;
output DM9000A_avalonS_reset_n;
output DM9000A_avalonS_wait_counter_eq_0;
output DM9000A_avalonS_write_n;
output [ 15: 0] DM9000A_avalonS_writedata;
output cpu_0_data_master_granted_DM9000A_avalonS;
output cpu_0_data_master_qualified_request_DM9000A_avalonS;
output cpu_0_data_master_read_data_valid_DM9000A_avalonS;
output cpu_0_data_master_requests_DM9000A_avalonS;
output d1_DM9000A_avalonS_end_xfer;
input DM9000A_avalonS_irq;
input [ 15: 0] DM9000A_avalonS_readdata;
input clk;
input [ 24: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input reset_n;
wire DM9000A_avalonS_address;
wire DM9000A_avalonS_allgrants;
wire DM9000A_avalonS_allow_new_arb_cycle;
wire DM9000A_avalonS_any_bursting_master_saved_grant;
wire DM9000A_avalonS_any_continuerequest;
wire DM9000A_avalonS_arb_counter_enable;
reg [ 2: 0] DM9000A_avalonS_arb_share_counter;
wire [ 2: 0] DM9000A_avalonS_arb_share_counter_next_value;
wire [ 2: 0] DM9000A_avalonS_arb_share_set_values;
wire DM9000A_avalonS_beginbursttransfer_internal;
wire DM9000A_avalonS_begins_xfer;
wire DM9000A_avalonS_chipselect_n;
wire DM9000A_avalonS_counter_load_value;
wire DM9000A_avalonS_end_xfer;
wire DM9000A_avalonS_firsttransfer;
wire DM9000A_avalonS_grant_vector;
wire DM9000A_avalonS_in_a_read_cycle;
wire DM9000A_avalonS_in_a_write_cycle;
wire DM9000A_avalonS_irq_from_sa;
wire DM9000A_avalonS_master_qreq_vector;
wire DM9000A_avalonS_non_bursting_master_requests;
wire DM9000A_avalonS_read_n;
wire [ 15: 0] DM9000A_avalonS_readdata_from_sa;
reg DM9000A_avalonS_reg_firsttransfer;
wire DM9000A_avalonS_reset_n;
reg DM9000A_avalonS_slavearbiterlockenable;
wire DM9000A_avalonS_slavearbiterlockenable2;
wire DM9000A_avalonS_unreg_firsttransfer;
reg DM9000A_avalonS_wait_counter;
wire DM9000A_avalonS_wait_counter_eq_0;
wire DM9000A_avalonS_waits_for_read;
wire DM9000A_avalonS_waits_for_write;
wire DM9000A_avalonS_write_n;
wire [ 15: 0] DM9000A_avalonS_writedata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_DM9000A_avalonS;
wire cpu_0_data_master_qualified_request_DM9000A_avalonS;
wire cpu_0_data_master_read_data_valid_DM9000A_avalonS;
wire cpu_0_data_master_requests_DM9000A_avalonS;
wire cpu_0_data_master_saved_grant_DM9000A_avalonS;
reg d1_DM9000A_avalonS_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_DM9000A_avalonS;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 24: 0] shifted_address_to_DM9000A_avalonS_from_cpu_0_data_master;
wire wait_for_DM9000A_avalonS_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~DM9000A_avalonS_end_xfer;
end
assign DM9000A_avalonS_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_DM9000A_avalonS));
//assign DM9000A_avalonS_readdata_from_sa = DM9000A_avalonS_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign DM9000A_avalonS_readdata_from_sa = DM9000A_avalonS_readdata;
assign cpu_0_data_master_requests_DM9000A_avalonS = ({cpu_0_data_master_address_to_slave[24 : 3] , 3'b0} == 25'h900090) & (cpu_0_data_master_read | cpu_0_data_master_write);
//DM9000A_avalonS_arb_share_counter set values, which is an e_mux
assign DM9000A_avalonS_arb_share_set_values = 1;
//DM9000A_avalonS_non_bursting_master_requests mux, which is an e_mux
assign DM9000A_avalonS_non_bursting_master_requests = cpu_0_data_master_requests_DM9000A_avalonS;
//DM9000A_avalonS_any_bursting_master_saved_grant mux, which is an e_mux
assign DM9000A_avalonS_any_bursting_master_saved_grant = 0;
//DM9000A_avalonS_arb_share_counter_next_value assignment, which is an e_assign
assign DM9000A_avalonS_arb_share_counter_next_value = DM9000A_avalonS_firsttransfer ? (DM9000A_avalonS_arb_share_set_values - 1) : |DM9000A_avalonS_arb_share_counter ? (DM9000A_avalonS_arb_share_counter - 1) : 0;
//DM9000A_avalonS_allgrants all slave grants, which is an e_mux
assign DM9000A_avalonS_allgrants = |DM9000A_avalonS_grant_vector;
//DM9000A_avalonS_end_xfer assignment, which is an e_assign
assign DM9000A_avalonS_end_xfer = ~(DM9000A_avalonS_waits_for_read | DM9000A_avalonS_waits_for_write);
//end_xfer_arb_share_counter_term_DM9000A_avalonS arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_DM9000A_avalonS = DM9000A_avalonS_end_xfer & (~DM9000A_avalonS_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//DM9000A_avalonS_arb_share_counter arbitration counter enable, which is an e_assign
assign DM9000A_avalonS_arb_counter_enable = (end_xfer_arb_share_counter_term_DM9000A_avalonS & DM9000A_avalonS_allgrants) | (end_xfer_arb_share_counter_term_DM9000A_avalonS & ~DM9000A_avalonS_non_bursting_master_requests);
//DM9000A_avalonS_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
DM9000A_avalonS_arb_share_counter <= 0;
else if (DM9000A_avalonS_arb_counter_enable)
DM9000A_avalonS_arb_share_counter <= DM9000A_avalonS_arb_share_counter_next_value;
end
//DM9000A_avalonS_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
DM9000A_avalonS_slavearbiterlockenable <= 0;
else if ((|DM9000A_avalonS_master_qreq_vector & end_xfer_arb_share_counter_term_DM9000A_avalonS) | (end_xfer_arb_share_counter_term_DM9000A_avalonS & ~DM9000A_avalonS_non_bursting_master_requests))
DM9000A_avalonS_slavearbiterlockenable <= |DM9000A_avalonS_arb_share_counter_next_value;
end
//cpu_0/data_master DM9000A/avalonS arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = DM9000A_avalonS_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//DM9000A_avalonS_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign DM9000A_avalonS_slavearbiterlockenable2 = |DM9000A_avalonS_arb_share_counter_next_value;
//cpu_0/data_master DM9000A/avalonS arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = DM9000A_avalonS_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//DM9000A_avalonS_any_continuerequest at least one master continues requesting, which is an e_assign
assign DM9000A_avalonS_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_DM9000A_avalonS = cpu_0_data_master_requests_DM9000A_avalonS;
//DM9000A_avalonS_writedata mux, which is an e_mux
assign DM9000A_avalonS_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_DM9000A_avalonS = cpu_0_data_master_qualified_request_DM9000A_avalonS;
//cpu_0/data_master saved-grant DM9000A/avalonS, which is an e_assign
assign cpu_0_data_master_saved_grant_DM9000A_avalonS = cpu_0_data_master_requests_DM9000A_avalonS;
//allow new arb cycle for DM9000A/avalonS, which is an e_assign
assign DM9000A_avalonS_allow_new_arb_cycle = 1;
//placeholder chosen master
assign DM9000A_avalonS_grant_vector = 1;
//placeholder vector of master qualified-requests
assign DM9000A_avalonS_master_qreq_vector = 1;
//DM9000A_avalonS_reset_n assignment, which is an e_assign
assign DM9000A_avalonS_reset_n = reset_n;
assign DM9000A_avalonS_chipselect_n = ~cpu_0_data_master_granted_DM9000A_avalonS;
//DM9000A_avalonS_firsttransfer first transaction, which is an e_assign
assign DM9000A_avalonS_firsttransfer = DM9000A_avalonS_begins_xfer ? DM9000A_avalonS_unreg_firsttransfer : DM9000A_avalonS_reg_firsttransfer;
//DM9000A_avalonS_unreg_firsttransfer first transaction, which is an e_assign
assign DM9000A_avalonS_unreg_firsttransfer = ~(DM9000A_avalonS_slavearbiterlockenable & DM9000A_avalonS_any_continuerequest);
//DM9000A_avalonS_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
DM9000A_avalonS_reg_firsttransfer <= 1'b1;
else if (DM9000A_avalonS_begins_xfer)
DM9000A_avalonS_reg_firsttransfer <= DM9000A_avalonS_unreg_firsttransfer;
end
//DM9000A_avalonS_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign DM9000A_avalonS_beginbursttransfer_internal = DM9000A_avalonS_begins_xfer;
//~DM9000A_avalonS_read_n assignment, which is an e_mux
assign DM9000A_avalonS_read_n = ~(((cpu_0_data_master_granted_DM9000A_avalonS & cpu_0_data_master_read))& ~DM9000A_avalonS_begins_xfer);
//~DM9000A_avalonS_write_n assignment, which is an e_mux
assign DM9000A_avalonS_write_n = ~(((cpu_0_data_master_granted_DM9000A_avalonS & cpu_0_data_master_write)) & ~DM9000A_avalonS_begins_xfer & (DM9000A_avalonS_wait_counter >= 1));
assign shifted_address_to_DM9000A_avalonS_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//DM9000A_avalonS_address mux, which is an e_mux
assign DM9000A_avalonS_address = shifted_address_to_DM9000A_avalonS_from_cpu_0_data_master >> 2;
//d1_DM9000A_avalonS_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_DM9000A_avalonS_end_xfer <= 1;
else
d1_DM9000A_avalonS_end_xfer <= DM9000A_avalonS_end_xfer;
end
//DM9000A_avalonS_waits_for_read in a cycle, which is an e_mux
assign DM9000A_avalonS_waits_for_read = DM9000A_avalonS_in_a_read_cycle & DM9000A_avalonS_begins_xfer;
//DM9000A_avalonS_in_a_read_cycle assignment, which is an e_assign
assign DM9000A_avalonS_in_a_read_cycle = cpu_0_data_master_granted_DM9000A_avalonS & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = DM9000A_avalonS_in_a_read_cycle;
//DM9000A_avalonS_waits_for_write in a cycle, which is an e_mux
assign DM9000A_avalonS_waits_for_write = DM9000A_avalonS_in_a_write_cycle & wait_for_DM9000A_avalonS_counter;
//DM9000A_avalonS_in_a_write_cycle assignment, which is an e_assign
assign DM9000A_avalonS_in_a_write_cycle = cpu_0_data_master_granted_DM9000A_avalonS & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = DM9000A_avalonS_in_a_write_cycle;
assign DM9000A_avalonS_wait_counter_eq_0 = DM9000A_avalonS_wait_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
DM9000A_avalonS_wait_counter <= 0;
else
DM9000A_avalonS_wait_counter <= DM9000A_avalonS_counter_load_value;
end
assign DM9000A_avalonS_counter_load_value = ((DM9000A_avalonS_in_a_write_cycle & DM9000A_avalonS_begins_xfer))? 1 :
(~DM9000A_avalonS_wait_counter_eq_0)? DM9000A_avalonS_wait_counter - 1 :
0;
assign wait_for_DM9000A_avalonS_counter = DM9000A_avalonS_begins_xfer | ~DM9000A_avalonS_wait_counter_eq_0;
//assign DM9000A_avalonS_irq_from_sa = DM9000A_avalonS_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign DM9000A_avalonS_irq_from_sa = DM9000A_avalonS_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//DM9000A/avalonS enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module I2C_0_avalonS_arbitrator (
// inputs:
I2C_0_avalonS_irq,
I2C_0_avalonS_readdata,
I2C_0_avalonS_waitrequest_n,
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
reset_n,
// outputs:
I2C_0_avalonS_address,
I2C_0_avalonS_always0,
I2C_0_avalonS_chipselect,
I2C_0_avalonS_irq_from_sa,
I2C_0_avalonS_readdata_from_sa,
I2C_0_avalonS_reset_n,
I2C_0_avalonS_waitrequest_n_from_sa,
I2C_0_avalonS_write,
I2C_0_avalonS_writedata,
cpu_0_data_master_granted_I2C_0_avalonS,
cpu_0_data_master_qualified_request_I2C_0_avalonS,
cpu_0_data_master_read_data_valid_I2C_0_avalonS,
cpu_0_data_master_requests_I2C_0_avalonS,
d1_I2C_0_avalonS_end_xfer
)
;
output [ 2: 0] I2C_0_avalonS_address;
output I2C_0_avalonS_always0;
output I2C_0_avalonS_chipselect;
output I2C_0_avalonS_irq_from_sa;
output [ 7: 0] I2C_0_avalonS_readdata_from_sa;
output I2C_0_avalonS_reset_n;
output I2C_0_avalonS_waitrequest_n_from_sa;
output I2C_0_avalonS_write;
output [ 7: 0] I2C_0_avalonS_writedata;
output cpu_0_data_master_granted_I2C_0_avalonS;
output cpu_0_data_master_qualified_request_I2C_0_avalonS;
output cpu_0_data_master_read_data_valid_I2C_0_avalonS;
output cpu_0_data_master_requests_I2C_0_avalonS;
output d1_I2C_0_avalonS_end_xfer;
input I2C_0_avalonS_irq;
input [ 7: 0] I2C_0_avalonS_readdata;
input I2C_0_avalonS_waitrequest_n;
input clk;
input [ 24: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input reset_n;
wire [ 2: 0] I2C_0_avalonS_address;
wire I2C_0_avalonS_allgrants;
wire I2C_0_avalonS_allow_new_arb_cycle;
wire I2C_0_avalonS_always0;
wire I2C_0_avalonS_any_bursting_master_saved_grant;
wire I2C_0_avalonS_any_continuerequest;
wire I2C_0_avalonS_arb_counter_enable;
reg [ 2: 0] I2C_0_avalonS_arb_share_counter;
wire [ 2: 0] I2C_0_avalonS_arb_share_counter_next_value;
wire [ 2: 0] I2C_0_avalonS_arb_share_set_values;
wire I2C_0_avalonS_beginbursttransfer_internal;
wire I2C_0_avalonS_begins_xfer;
wire I2C_0_avalonS_chipselect;
wire I2C_0_avalonS_end_xfer;
wire I2C_0_avalonS_firsttransfer;
wire I2C_0_avalonS_grant_vector;
wire I2C_0_avalonS_in_a_read_cycle;
wire I2C_0_avalonS_in_a_write_cycle;
wire I2C_0_avalonS_irq_from_sa;
wire I2C_0_avalonS_master_qreq_vector;
wire I2C_0_avalonS_non_bursting_master_requests;
wire I2C_0_avalonS_pretend_byte_enable;
wire [ 7: 0] I2C_0_avalonS_readdata_from_sa;
reg I2C_0_avalonS_reg_firsttransfer;
wire I2C_0_avalonS_reset_n;
reg I2C_0_avalonS_slavearbiterlockenable;
wire I2C_0_avalonS_slavearbiterlockenable2;
wire I2C_0_avalonS_unreg_firsttransfer;
wire I2C_0_avalonS_waitrequest_n_from_sa;
wire I2C_0_avalonS_waits_for_read;
wire I2C_0_avalonS_waits_for_write;
wire I2C_0_avalonS_write;
wire [ 7: 0] I2C_0_avalonS_writedata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_I2C_0_avalonS;
wire cpu_0_data_master_qualified_request_I2C_0_avalonS;
wire cpu_0_data_master_read_data_valid_I2C_0_avalonS;
wire cpu_0_data_master_requests_I2C_0_avalonS;
wire cpu_0_data_master_saved_grant_I2C_0_avalonS;
reg d1_I2C_0_avalonS_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_I2C_0_avalonS;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 24: 0] shifted_address_to_I2C_0_avalonS_from_cpu_0_data_master;
wire wait_for_I2C_0_avalonS_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~I2C_0_avalonS_end_xfer;
end
assign I2C_0_avalonS_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_I2C_0_avalonS));
//assign I2C_0_avalonS_readdata_from_sa = I2C_0_avalonS_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign I2C_0_avalonS_readdata_from_sa = I2C_0_avalonS_readdata;
assign cpu_0_data_master_requests_I2C_0_avalonS = ({cpu_0_data_master_address_to_slave[24 : 5] , 5'b0} == 25'h900100) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign I2C_0_avalonS_waitrequest_n_from_sa = I2C_0_avalonS_waitrequest_n so that symbol knows where to group signals which may go to master only, which is an e_assign
assign I2C_0_avalonS_waitrequest_n_from_sa = I2C_0_avalonS_waitrequest_n;
//I2C_0_avalonS_arb_share_counter set values, which is an e_mux
assign I2C_0_avalonS_arb_share_set_values = 1;
//I2C_0_avalonS_non_bursting_master_requests mux, which is an e_mux
assign I2C_0_avalonS_non_bursting_master_requests = cpu_0_data_master_requests_I2C_0_avalonS;
//I2C_0_avalonS_any_bursting_master_saved_grant mux, which is an e_mux
assign I2C_0_avalonS_any_bursting_master_saved_grant = 0;
//I2C_0_avalonS_arb_share_counter_next_value assignment, which is an e_assign
assign I2C_0_avalonS_arb_share_counter_next_value = I2C_0_avalonS_firsttransfer ? (I2C_0_avalonS_arb_share_set_values - 1) : |I2C_0_avalonS_arb_share_counter ? (I2C_0_avalonS_arb_share_counter - 1) : 0;
//I2C_0_avalonS_allgrants all slave grants, which is an e_mux
assign I2C_0_avalonS_allgrants = |I2C_0_avalonS_grant_vector;
//I2C_0_avalonS_end_xfer assignment, which is an e_assign
assign I2C_0_avalonS_end_xfer = ~(I2C_0_avalonS_waits_for_read | I2C_0_avalonS_waits_for_write);
//end_xfer_arb_share_counter_term_I2C_0_avalonS arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_I2C_0_avalonS = I2C_0_avalonS_end_xfer & (~I2C_0_avalonS_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//I2C_0_avalonS_arb_share_counter arbitration counter enable, which is an e_assign
assign I2C_0_avalonS_arb_counter_enable = (end_xfer_arb_share_counter_term_I2C_0_avalonS & I2C_0_avalonS_allgrants) | (end_xfer_arb_share_counter_term_I2C_0_avalonS & ~I2C_0_avalonS_non_bursting_master_requests);
//I2C_0_avalonS_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
I2C_0_avalonS_arb_share_counter <= 0;
else if (I2C_0_avalonS_arb_counter_enable)
I2C_0_avalonS_arb_share_counter <= I2C_0_avalonS_arb_share_counter_next_value;
end
//I2C_0_avalonS_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
I2C_0_avalonS_slavearbiterlockenable <= 0;
else if ((|I2C_0_avalonS_master_qreq_vector & end_xfer_arb_share_counter_term_I2C_0_avalonS) | (end_xfer_arb_share_counter_term_I2C_0_avalonS & ~I2C_0_avalonS_non_bursting_master_requests))
I2C_0_avalonS_slavearbiterlockenable <= |I2C_0_avalonS_arb_share_counter_next_value;
end
//cpu_0/data_master I2C_0/avalonS arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = I2C_0_avalonS_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//I2C_0_avalonS_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign I2C_0_avalonS_slavearbiterlockenable2 = |I2C_0_avalonS_arb_share_counter_next_value;
//cpu_0/data_master I2C_0/avalonS arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = I2C_0_avalonS_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//I2C_0_avalonS_any_continuerequest at least one master continues requesting, which is an e_assign
assign I2C_0_avalonS_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_I2C_0_avalonS = cpu_0_data_master_requests_I2C_0_avalonS & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest)) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//I2C_0_avalonS_writedata mux, which is an e_mux
assign I2C_0_avalonS_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_I2C_0_avalonS = cpu_0_data_master_qualified_request_I2C_0_avalonS;
//cpu_0/data_master saved-grant I2C_0/avalonS, which is an e_assign
assign cpu_0_data_master_saved_grant_I2C_0_avalonS = cpu_0_data_master_requests_I2C_0_avalonS;
//allow new arb cycle for I2C_0/avalonS, which is an e_assign
assign I2C_0_avalonS_allow_new_arb_cycle = 1;
//placeholder chosen master
assign I2C_0_avalonS_grant_vector = 1;
//placeholder vector of master qualified-requests
assign I2C_0_avalonS_master_qreq_vector = 1;
//I2C_0_avalonS_reset_n assignment, which is an e_assign
assign I2C_0_avalonS_reset_n = reset_n;
assign I2C_0_avalonS_chipselect = cpu_0_data_master_granted_I2C_0_avalonS;
//I2C_0_avalonS_firsttransfer first transaction, which is an e_assign
assign I2C_0_avalonS_firsttransfer = I2C_0_avalonS_begins_xfer ? I2C_0_avalonS_unreg_firsttransfer : I2C_0_avalonS_reg_firsttransfer;
//I2C_0_avalonS_unreg_firsttransfer first transaction, which is an e_assign
assign I2C_0_avalonS_unreg_firsttransfer = ~(I2C_0_avalonS_slavearbiterlockenable & I2C_0_avalonS_any_continuerequest);
//I2C_0_avalonS_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
I2C_0_avalonS_reg_firsttransfer <= 1'b1;
else if (I2C_0_avalonS_begins_xfer)
I2C_0_avalonS_reg_firsttransfer <= I2C_0_avalonS_unreg_firsttransfer;
end
//I2C_0_avalonS_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign I2C_0_avalonS_beginbursttransfer_internal = I2C_0_avalonS_begins_xfer;
//I2C_0_avalonS_write assignment, which is an e_mux
assign I2C_0_avalonS_write = ((cpu_0_data_master_granted_I2C_0_avalonS & cpu_0_data_master_write)) & I2C_0_avalonS_pretend_byte_enable;
assign shifted_address_to_I2C_0_avalonS_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//I2C_0_avalonS_address mux, which is an e_mux
assign I2C_0_avalonS_address = shifted_address_to_I2C_0_avalonS_from_cpu_0_data_master >> 2;
//d1_I2C_0_avalonS_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_I2C_0_avalonS_end_xfer <= 1;
else
d1_I2C_0_avalonS_end_xfer <= I2C_0_avalonS_end_xfer;
end
//I2C_0_avalonS_waits_for_read in a cycle, which is an e_mux
assign I2C_0_avalonS_waits_for_read = I2C_0_avalonS_in_a_read_cycle & ~I2C_0_avalonS_waitrequest_n_from_sa;
//I2C_0_avalonS_in_a_read_cycle assignment, which is an e_assign
assign I2C_0_avalonS_in_a_read_cycle = cpu_0_data_master_granted_I2C_0_avalonS & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = I2C_0_avalonS_in_a_read_cycle;
//I2C_0_avalonS_waits_for_write in a cycle, which is an e_mux
assign I2C_0_avalonS_waits_for_write = I2C_0_avalonS_in_a_write_cycle & ~I2C_0_avalonS_waitrequest_n_from_sa;
//I2C_0_avalonS_in_a_write_cycle assignment, which is an e_assign
assign I2C_0_avalonS_in_a_write_cycle = cpu_0_data_master_granted_I2C_0_avalonS & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = I2C_0_avalonS_in_a_write_cycle;
assign wait_for_I2C_0_avalonS_counter = 0;
//I2C_0_avalonS_pretend_byte_enable byte enable port mux, which is an e_mux
assign I2C_0_avalonS_pretend_byte_enable = (cpu_0_data_master_granted_I2C_0_avalonS)? cpu_0_data_master_byteenable :
-1;
//I2C_0_avalonS_always0 always signal, which is an e_assign
assign I2C_0_avalonS_always0 = 0;
//assign I2C_0_avalonS_irq_from_sa = I2C_0_avalonS_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign I2C_0_avalonS_irq_from_sa = I2C_0_avalonS_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//I2C_0/avalonS enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ISP1362_avalonS_arbitrator (
// inputs:
ISP1362_avalonS_irq_n,
ISP1362_avalonS_readdata,
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
reset_n,
// outputs:
ISP1362_avalonS_address,
ISP1362_avalonS_chipselect_n,
ISP1362_avalonS_irq_n_from_sa,
ISP1362_avalonS_read_n,
ISP1362_avalonS_readdata_from_sa,
ISP1362_avalonS_wait_counter_eq_0,
ISP1362_avalonS_wait_counter_eq_1,
ISP1362_avalonS_write_n,
ISP1362_avalonS_writedata,
cpu_0_data_master_granted_ISP1362_avalonS,
cpu_0_data_master_qualified_request_ISP1362_avalonS,
cpu_0_data_master_read_data_valid_ISP1362_avalonS,
cpu_0_data_master_requests_ISP1362_avalonS,
d1_ISP1362_avalonS_end_xfer
)
;
output [ 1: 0] ISP1362_avalonS_address;
output ISP1362_avalonS_chipselect_n;
output ISP1362_avalonS_irq_n_from_sa;
output ISP1362_avalonS_read_n;
output [ 15: 0] ISP1362_avalonS_readdata_from_sa;
output ISP1362_avalonS_wait_counter_eq_0;
output ISP1362_avalonS_wait_counter_eq_1;
output ISP1362_avalonS_write_n;
output [ 15: 0] ISP1362_avalonS_writedata;
output cpu_0_data_master_granted_ISP1362_avalonS;
output cpu_0_data_master_qualified_request_ISP1362_avalonS;
output cpu_0_data_master_read_data_valid_ISP1362_avalonS;
output cpu_0_data_master_requests_ISP1362_avalonS;
output d1_ISP1362_avalonS_end_xfer;
input ISP1362_avalonS_irq_n;
input [ 15: 0] ISP1362_avalonS_readdata;
input clk;
input [ 24: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input reset_n;
wire [ 1: 0] ISP1362_avalonS_address;
wire ISP1362_avalonS_allgrants;
wire ISP1362_avalonS_allow_new_arb_cycle;
wire ISP1362_avalonS_any_bursting_master_saved_grant;
wire ISP1362_avalonS_any_continuerequest;
wire ISP1362_avalonS_arb_counter_enable;
reg [ 2: 0] ISP1362_avalonS_arb_share_counter;
wire [ 2: 0] ISP1362_avalonS_arb_share_counter_next_value;
wire [ 2: 0] ISP1362_avalonS_arb_share_set_values;
wire ISP1362_avalonS_beginbursttransfer_internal;
wire ISP1362_avalonS_begins_xfer;
wire ISP1362_avalonS_chipselect_n;
wire [ 4: 0] ISP1362_avalonS_counter_load_value;
wire ISP1362_avalonS_end_xfer;
wire ISP1362_avalonS_firsttransfer;
wire ISP1362_avalonS_grant_vector;
wire ISP1362_avalonS_in_a_read_cycle;
wire ISP1362_avalonS_in_a_write_cycle;
wire ISP1362_avalonS_irq_n_from_sa;
wire ISP1362_avalonS_master_qreq_vector;
wire ISP1362_avalonS_non_bursting_master_requests;
wire ISP1362_avalonS_read_n;
wire [ 15: 0] ISP1362_avalonS_readdata_from_sa;
reg ISP1362_avalonS_reg_firsttransfer;
reg ISP1362_avalonS_slavearbiterlockenable;
wire ISP1362_avalonS_slavearbiterlockenable2;
wire ISP1362_avalonS_unreg_firsttransfer;
reg [ 4: 0] ISP1362_avalonS_wait_counter;
wire ISP1362_avalonS_wait_counter_eq_0;
wire ISP1362_avalonS_wait_counter_eq_1;
wire ISP1362_avalonS_waits_for_read;
wire ISP1362_avalonS_waits_for_write;
wire ISP1362_avalonS_write_n;
wire [ 15: 0] ISP1362_avalonS_writedata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_ISP1362_avalonS;
wire cpu_0_data_master_qualified_request_ISP1362_avalonS;
wire cpu_0_data_master_read_data_valid_ISP1362_avalonS;
wire cpu_0_data_master_requests_ISP1362_avalonS;
wire cpu_0_data_master_saved_grant_ISP1362_avalonS;
reg d1_ISP1362_avalonS_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_ISP1362_avalonS;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 24: 0] shifted_address_to_ISP1362_avalonS_from_cpu_0_data_master;
wire wait_for_ISP1362_avalonS_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~ISP1362_avalonS_end_xfer;
end
assign ISP1362_avalonS_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_ISP1362_avalonS));
//assign ISP1362_avalonS_readdata_from_sa = ISP1362_avalonS_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign ISP1362_avalonS_readdata_from_sa = ISP1362_avalonS_readdata;
assign cpu_0_data_master_requests_ISP1362_avalonS = ({cpu_0_data_master_address_to_slave[24 : 4] , 4'b0} == 25'h900080) & (cpu_0_data_master_read | cpu_0_data_master_write);
//ISP1362_avalonS_arb_share_counter set values, which is an e_mux
assign ISP1362_avalonS_arb_share_set_values = 1;
//ISP1362_avalonS_non_bursting_master_requests mux, which is an e_mux
assign ISP1362_avalonS_non_bursting_master_requests = cpu_0_data_master_requests_ISP1362_avalonS;
//ISP1362_avalonS_any_bursting_master_saved_grant mux, which is an e_mux
assign ISP1362_avalonS_any_bursting_master_saved_grant = 0;
//ISP1362_avalonS_arb_share_counter_next_value assignment, which is an e_assign
assign ISP1362_avalonS_arb_share_counter_next_value = ISP1362_avalonS_firsttransfer ? (ISP1362_avalonS_arb_share_set_values - 1) : |ISP1362_avalonS_arb_share_counter ? (ISP1362_avalonS_arb_share_counter - 1) : 0;
//ISP1362_avalonS_allgrants all slave grants, which is an e_mux
assign ISP1362_avalonS_allgrants = |ISP1362_avalonS_grant_vector;
//ISP1362_avalonS_end_xfer assignment, which is an e_assign
assign ISP1362_avalonS_end_xfer = ~(ISP1362_avalonS_waits_for_read | ISP1362_avalonS_waits_for_write);
//end_xfer_arb_share_counter_term_ISP1362_avalonS arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_ISP1362_avalonS = ISP1362_avalonS_end_xfer & (~ISP1362_avalonS_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//ISP1362_avalonS_arb_share_counter arbitration counter enable, which is an e_assign
assign ISP1362_avalonS_arb_counter_enable = (end_xfer_arb_share_counter_term_ISP1362_avalonS & ISP1362_avalonS_allgrants) | (end_xfer_arb_share_counter_term_ISP1362_avalonS & ~ISP1362_avalonS_non_bursting_master_requests);
//ISP1362_avalonS_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
ISP1362_avalonS_arb_share_counter <= 0;
else if (ISP1362_avalonS_arb_counter_enable)
ISP1362_avalonS_arb_share_counter <= ISP1362_avalonS_arb_share_counter_next_value;
end
//ISP1362_avalonS_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
ISP1362_avalonS_slavearbiterlockenable <= 0;
else if ((|ISP1362_avalonS_master_qreq_vector & end_xfer_arb_share_counter_term_ISP1362_avalonS) | (end_xfer_arb_share_counter_term_ISP1362_avalonS & ~ISP1362_avalonS_non_bursting_master_requests))
ISP1362_avalonS_slavearbiterlockenable <= |ISP1362_avalonS_arb_share_counter_next_value;
end
//cpu_0/data_master ISP1362/avalonS arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = ISP1362_avalonS_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//ISP1362_avalonS_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign ISP1362_avalonS_slavearbiterlockenable2 = |ISP1362_avalonS_arb_share_counter_next_value;
//cpu_0/data_master ISP1362/avalonS arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = ISP1362_avalonS_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//ISP1362_avalonS_any_continuerequest at least one master continues requesting, which is an e_assign
assign ISP1362_avalonS_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_ISP1362_avalonS = cpu_0_data_master_requests_ISP1362_avalonS;
//ISP1362_avalonS_writedata mux, which is an e_mux
assign ISP1362_avalonS_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_ISP1362_avalonS = cpu_0_data_master_qualified_request_ISP1362_avalonS;
//cpu_0/data_master saved-grant ISP1362/avalonS, which is an e_assign
assign cpu_0_data_master_saved_grant_ISP1362_avalonS = cpu_0_data_master_requests_ISP1362_avalonS;
//allow new arb cycle for ISP1362/avalonS, which is an e_assign
assign ISP1362_avalonS_allow_new_arb_cycle = 1;
//placeholder chosen master
assign ISP1362_avalonS_grant_vector = 1;
//placeholder vector of master qualified-requests
assign ISP1362_avalonS_master_qreq_vector = 1;
assign ISP1362_avalonS_chipselect_n = ~cpu_0_data_master_granted_ISP1362_avalonS;
//ISP1362_avalonS_firsttransfer first transaction, which is an e_assign
assign ISP1362_avalonS_firsttransfer = ISP1362_avalonS_begins_xfer ? ISP1362_avalonS_unreg_firsttransfer : ISP1362_avalonS_reg_firsttransfer;
//ISP1362_avalonS_unreg_firsttransfer first transaction, which is an e_assign
assign ISP1362_avalonS_unreg_firsttransfer = ~(ISP1362_avalonS_slavearbiterlockenable & ISP1362_avalonS_any_continuerequest);
//ISP1362_avalonS_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
ISP1362_avalonS_reg_firsttransfer <= 1'b1;
else if (ISP1362_avalonS_begins_xfer)
ISP1362_avalonS_reg_firsttransfer <= ISP1362_avalonS_unreg_firsttransfer;
end
//ISP1362_avalonS_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign ISP1362_avalonS_beginbursttransfer_internal = ISP1362_avalonS_begins_xfer;
//~ISP1362_avalonS_read_n assignment, which is an e_mux
assign ISP1362_avalonS_read_n = ~(((cpu_0_data_master_granted_ISP1362_avalonS & cpu_0_data_master_read))& ~ISP1362_avalonS_begins_xfer & (ISP1362_avalonS_wait_counter < 5));
//~ISP1362_avalonS_write_n assignment, which is an e_mux
assign ISP1362_avalonS_write_n = ~(((cpu_0_data_master_granted_ISP1362_avalonS & cpu_0_data_master_write)) & ~ISP1362_avalonS_begins_xfer & (ISP1362_avalonS_wait_counter >= 10) & (ISP1362_avalonS_wait_counter < 15));
assign shifted_address_to_ISP1362_avalonS_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//ISP1362_avalonS_address mux, which is an e_mux
assign ISP1362_avalonS_address = shifted_address_to_ISP1362_avalonS_from_cpu_0_data_master >> 2;
//d1_ISP1362_avalonS_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_ISP1362_avalonS_end_xfer <= 1;
else
d1_ISP1362_avalonS_end_xfer <= ISP1362_avalonS_end_xfer;
end
//ISP1362_avalonS_wait_counter_eq_1 assignment, which is an e_assign
assign ISP1362_avalonS_wait_counter_eq_1 = ISP1362_avalonS_wait_counter == 1;
//ISP1362_avalonS_waits_for_read in a cycle, which is an e_mux
assign ISP1362_avalonS_waits_for_read = ISP1362_avalonS_in_a_read_cycle & wait_for_ISP1362_avalonS_counter;
//ISP1362_avalonS_in_a_read_cycle assignment, which is an e_assign
assign ISP1362_avalonS_in_a_read_cycle = cpu_0_data_master_granted_ISP1362_avalonS & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = ISP1362_avalonS_in_a_read_cycle;
//ISP1362_avalonS_waits_for_write in a cycle, which is an e_mux
assign ISP1362_avalonS_waits_for_write = ISP1362_avalonS_in_a_write_cycle & wait_for_ISP1362_avalonS_counter;
//ISP1362_avalonS_in_a_write_cycle assignment, which is an e_assign
assign ISP1362_avalonS_in_a_write_cycle = cpu_0_data_master_granted_ISP1362_avalonS & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = ISP1362_avalonS_in_a_write_cycle;
assign ISP1362_avalonS_wait_counter_eq_0 = ISP1362_avalonS_wait_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
ISP1362_avalonS_wait_counter <= 0;
else
ISP1362_avalonS_wait_counter <= ISP1362_avalonS_counter_load_value;
end
assign ISP1362_avalonS_counter_load_value = ((ISP1362_avalonS_in_a_write_cycle & ISP1362_avalonS_begins_xfer))? 23 :
((ISP1362_avalonS_in_a_read_cycle & ISP1362_avalonS_begins_xfer))? 13 :
(~ISP1362_avalonS_wait_counter_eq_0)? ISP1362_avalonS_wait_counter - 1 :
0;
assign wait_for_ISP1362_avalonS_counter = ISP1362_avalonS_begins_xfer | ~ISP1362_avalonS_wait_counter_eq_0;
//assign ISP1362_avalonS_irq_n_from_sa = ISP1362_avalonS_irq_n so that symbol knows where to group signals which may go to master only, which is an e_assign
assign ISP1362_avalonS_irq_n_from_sa = ISP1362_avalonS_irq_n;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//ISP1362/avalonS enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SEG7_Display_avalonS_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
reset_n,
// outputs:
SEG7_Display_avalonS_reset_n,
SEG7_Display_avalonS_write,
SEG7_Display_avalonS_writedata,
cpu_0_data_master_granted_SEG7_Display_avalonS,
cpu_0_data_master_qualified_request_SEG7_Display_avalonS,
cpu_0_data_master_read_data_valid_SEG7_Display_avalonS,
cpu_0_data_master_requests_SEG7_Display_avalonS,
d1_SEG7_Display_avalonS_end_xfer
)
;
output SEG7_Display_avalonS_reset_n;
output SEG7_Display_avalonS_write;
output [ 31: 0] SEG7_Display_avalonS_writedata;
output cpu_0_data_master_granted_SEG7_Display_avalonS;
output cpu_0_data_master_qualified_request_SEG7_Display_avalonS;
output cpu_0_data_master_read_data_valid_SEG7_Display_avalonS;
output cpu_0_data_master_requests_SEG7_Display_avalonS;
output d1_SEG7_Display_avalonS_end_xfer;
input clk;
input [ 24: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input reset_n;
wire SEG7_Display_avalonS_allgrants;
wire SEG7_Display_avalonS_allow_new_arb_cycle;
wire SEG7_Display_avalonS_any_bursting_master_saved_grant;
wire SEG7_Display_avalonS_any_continuerequest;
wire SEG7_Display_avalonS_arb_counter_enable;
reg [ 2: 0] SEG7_Display_avalonS_arb_share_counter;
wire [ 2: 0] SEG7_Display_avalonS_arb_share_counter_next_value;
wire [ 2: 0] SEG7_Display_avalonS_arb_share_set_values;
wire SEG7_Display_avalonS_beginbursttransfer_internal;
wire SEG7_Display_avalonS_begins_xfer;
wire SEG7_Display_avalonS_end_xfer;
wire SEG7_Display_avalonS_firsttransfer;
wire SEG7_Display_avalonS_grant_vector;
wire SEG7_Display_avalonS_in_a_read_cycle;
wire SEG7_Display_avalonS_in_a_write_cycle;
wire SEG7_Display_avalonS_master_qreq_vector;
wire SEG7_Display_avalonS_non_bursting_master_requests;
reg SEG7_Display_avalonS_reg_firsttransfer;
wire SEG7_Display_avalonS_reset_n;
reg SEG7_Display_avalonS_slavearbiterlockenable;
wire SEG7_Display_avalonS_slavearbiterlockenable2;
wire SEG7_Display_avalonS_unreg_firsttransfer;
wire SEG7_Display_avalonS_waits_for_read;
wire SEG7_Display_avalonS_waits_for_write;
wire SEG7_Display_avalonS_write;
wire [ 31: 0] SEG7_Display_avalonS_writedata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_SEG7_Display_avalonS;
wire cpu_0_data_master_qualified_request_SEG7_Display_avalonS;
wire cpu_0_data_master_read_data_valid_SEG7_Display_avalonS;