Add rust hdl #360 (#441)

Author: zoomer-k

CHANGELOG.md

@@ -4,6 +4,12 @@ All notable changes to this project will be documented in this file.
 
 The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
 
+## [Unreleased]
+
+### Added
+
+- Add support for [rust_hdl](https://github.com/VHDL-LS/rust_hdl) Language Server. [#360](https://github.com/mshr-h/vscode-verilog-hdl-support/issues/360)
+
 ## [1.12.0] - 2023-08-14
 
 - Update README.md for ctags [#433](https://github.com/mshr-h/vscode-verilog-hdl-support/pull/433)
@@ -55,7 +61,7 @@ The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
 
 ### Fixed
 
-- Fixed Slang & Verilator: cant run under WSL  [#418](https://github.com/mshr-h/vscode-verilog-hdl-support/issues/418)
+- Fixed Slang & Verilator: cant run under WSL [#418](https://github.com/mshr-h/vscode-verilog-hdl-support/issues/418)
 - Fixed [#139](https://github.com/mshr-h/vscode-verilog-hdl-support/issues/139)
 
 ## [1.11.4] - 2023-04-19

README.md

@@ -42,6 +42,7 @@ Install it from [VS Code Marketplace](https://marketplace.visualstudio.com/items
   - [veridian](https://github.com/vivekmalneedi/veridian)
   - [HDL Checker](https://github.com/suoto/hdl_checker)
   - [verible-verilog-ls](https://github.com/chipsalliance/verible)
+  - [rust_hdl](https://github.com/VHDL-LS/rust_hdl)
 - \[Experimental\] Formatting support from:
   - [verilog-format](https://github.com/ericsonj/verilog-format)
   - [istyle-verilog-formatter](https://github.com/thomasrussellmurphy/istyle-verilog-formatter)
@@ -103,6 +104,8 @@ If you encounter any problems even if it's not related to this feature, **deleti
 | [veridian](https://github.com/vivekmalneedi/veridian)          | not supported | enabled       | not supported |
 | [HDL Checker](https://github.com/suoto/hdl_checker)            | enabled       | enabled       | enabled       |
 | [verible-verilog-ls](https://github.com/chipsalliance/verible) | not supported | enabled       | not supported |
+| [rust_hdl](https://github.com/VHDL-LS/rust_hdl)                | not supported | not supported | enabled       |
+
 ### Formatting (Experimental)
 
 We currently support Verilog-HDL file formatting with the following formatters.
@@ -153,7 +156,7 @@ Use the following settings to configure the extension to your needs.
     Add custom work library to Modelsim for linting.
 
 - `verilog.linting.slang.arguments` (Default: nothing)
-  
+
     Add Slang arguments here (like macros). They will be added to Slang while linting (The command \"-I=<document folder>\" will be added by the linter by default).
 
 - `verilog.linting.slang.includePath` (Default: nothing)
@@ -238,6 +241,14 @@ Use the following settings to configure the extension to your needs.
 
     \[Experimental\] A path to the verible-verilog-ls Language Server binary.
 
+- `verilog.languageServer.rustHdl.enabled` (Default: `false`)
+
+    \[Experimental\] Enable rust_hdl Language Server for VHDL.
+
+- `verilog.languageServer.rustHdl.path` (Default: `vhdl_ls`)
+
+    \[Experimental\] A path to the rust_hdl Language Server binary.
+
 - `verilog.formatting.verilogHDL.formatter` (Default: `verilog-format`)
 
     \[Experimental\] Choose the Verilog-HDL formatter. Possible values are:

package.json

@@ -437,6 +437,18 @@
           "default": "hdl_checker",
           "description": "[Experimental] A path to the HDL Checker Language Server binary."
         },
+        "verilog.languageServer.rustHdl.enabled": {
+          "scope": "window",
+          "type": "boolean",
+          "default": false,
+          "description": "[Experimental] Enable Rust hdl Language Server for VHDL."
+        },
+        "verilog.languageServer.rustHdl.path": {
+          "scope": "window",
+          "type": "string",
+          "default": "vhdl_ls",
+          "description": "[Experimental] A path to the Rust hdl Language Server binary."
+        },
         "verilog.formatting.verilogHDL.formatter": {
           "scope": "window",
           "type": "string",

src/extension.ts

@@ -242,6 +242,11 @@ function initAllLanguageClients() {
   setupLanguageClient('veribleVerilogLs', 'verible-verilog-ls', [], [], {
     documentSelector: [{ scheme: 'file', language: 'systemverilog' }],
   });
+
+  // init rustHdl
+  setupLanguageClient('rustHdl', 'vhdl_ls', [], [], {
+    documentSelector: [{ scheme: 'file', language: 'vhdl' }],
+  });
 }
 
 function stopAllLanguageClients(): Promise<any> {