[BUG] A '\t' is inserted unexpectedly when instantiating verilog modules

[RickyTino]

Describe the bug
Actually I am not quite sure if it is a bug or a feature. The plugin always insert a "\t" in front of the first signal connection when using the "module instantiation" provided by this plugin.

Environment (please complete the following information):

• OS: Linux version 3.10.0-1160.105.1.el7.x86_64 (mockbuild@kbuilder.bsys.centos.org) (gcc version 4.8.5 20150623 (Red Hat 4.8.5-44) (GCC) )
• VS Code version 1.76.1
• Extension version v1.11.3

Steps to reproduce
Steps to reproduce the behavior:

1. In certain source file press alt+i
2. Select any SV module to instantiate
3. See a tab '\t' appear in front of the first signal connection

Expected behavior
No '\t' at all, or provide an option to set whether there be a '\t'

Actual behavior

Additional context
N/A

[RickyTino]

This problem also exists in v1.13.0 - recently tested

[mshr-h]

Please include repro.

[RickyTino]

Please include repro.

Steps described above, but I have some new findings. latest update below:
(Let's assume this file uses 4 spaces for indentation)

1. In certain .sv source file, press 'tab' key to produce a 4-space indent;
2. press alt+i (or ctrl+shift+p, then choose "Verilog: Instantiate Module")
3. Select a .sv file to instantiate. This file should contain a module with parameter.
4. See a tab character '\t' appear in front of the first signal connection

I think this time I've made it detailed enough though :)
And thanks for replying, I like your extension, saved a lot of my time!