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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT |
| 2 | + |
| 3 | +/dts-v1/; |
| 4 | +#include "mt7981b-cmcc-rax3000m.dts" |
| 5 | + |
| 6 | +/ { |
| 7 | + model = "CMCC RAX3000M NAND version (custom U-Boot layout)"; |
| 8 | + compatible = "cmcc,rax3000m-nand-ubootmod", "mediatek,mt7981"; |
| 9 | + |
| 10 | + aliases { |
| 11 | + label-mac-device = &gmac1; |
| 12 | + }; |
| 13 | +}; |
| 14 | + |
| 15 | +&gmac0 { |
| 16 | + nvmem-cells = <&macaddr_factory_2a 0>; |
| 17 | + nvmem-cell-names = "mac-address"; |
| 18 | +}; |
| 19 | + |
| 20 | +&gmac1 { |
| 21 | + nvmem-cells = <&macaddr_factory_24 0>; |
| 22 | + nvmem-cell-names = "mac-address"; |
| 23 | +}; |
| 24 | + |
| 25 | +&spi0 { |
| 26 | + pinctrl-names = "default"; |
| 27 | + pinctrl-0 = <&spi0_flash_pins>; |
| 28 | + status = "okay"; |
| 29 | + |
| 30 | + spi_nand: flash@0 { |
| 31 | + #address-cells = <1>; |
| 32 | + #size-cells = <1>; |
| 33 | + compatible = "spi-nand"; |
| 34 | + reg = <0>; |
| 35 | + |
| 36 | + spi-max-frequency = <52000000>; |
| 37 | + spi-tx-bus-width = <4>; |
| 38 | + spi-rx-bus-width = <4>; |
| 39 | + mediatek,nmbm; |
| 40 | + mediatek,bmt-max-ratio = <1>; |
| 41 | + mediatek,bmt-max-reserved-blocks = <64>; |
| 42 | + |
| 43 | + partitions: partitions { |
| 44 | + compatible = "fixed-partitions"; |
| 45 | + #address-cells = <1>; |
| 46 | + #size-cells = <1>; |
| 47 | + |
| 48 | + partition@0 { |
| 49 | + label = "BL2"; |
| 50 | + reg = <0x00000 0x100000>; |
| 51 | + read-only; |
| 52 | + }; |
| 53 | + |
| 54 | + partition@100000 { |
| 55 | + label = "u-boot-env"; |
| 56 | + reg = <0x100000 0x80000>; |
| 57 | + }; |
| 58 | + |
| 59 | + factory: partition@180000 { |
| 60 | + label = "Factory"; |
| 61 | + reg = <0x180000 0x200000>; |
| 62 | + |
| 63 | + compatible = "nvmem-cells"; |
| 64 | + nvmem-layout { |
| 65 | + compatible = "fixed-layout"; |
| 66 | + #address-cells = <1>; |
| 67 | + #size-cells = <1>; |
| 68 | + |
| 69 | + macaddr_factory_24: macaddr@24 { |
| 70 | + compatible = "mac-base"; |
| 71 | + reg = <0x24 0x6>; |
| 72 | + #nvmem-cell-cells = <1>; |
| 73 | + }; |
| 74 | + |
| 75 | + macaddr_factory_2a: macaddr@2a { |
| 76 | + compatible = "mac-base"; |
| 77 | + reg = <0x2a 0x6>; |
| 78 | + #nvmem-cell-cells = <1>; |
| 79 | + }; |
| 80 | + }; |
| 81 | + }; |
| 82 | + |
| 83 | + partition@380000 { |
| 84 | + label = "FIP"; |
| 85 | + reg = <0x380000 0x200000>; |
| 86 | + }; |
| 87 | + |
| 88 | + partition@580000 { |
| 89 | + label = "ubi"; |
| 90 | + reg = <0x580000 0x7200000>; |
| 91 | + }; |
| 92 | + }; |
| 93 | + }; |
| 94 | +}; |
| 95 | + |
| 96 | +&pio { |
| 97 | + spi0_flash_pins: spi0-pins { |
| 98 | + mux { |
| 99 | + function = "spi"; |
| 100 | + groups = "spi0", "spi0_wp_hold"; |
| 101 | + }; |
| 102 | + |
| 103 | + conf-pu { |
| 104 | + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; |
| 105 | + drive-strength = <MTK_DRIVE_8mA>; |
| 106 | + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; |
| 107 | + }; |
| 108 | + |
| 109 | + conf-pd { |
| 110 | + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; |
| 111 | + drive-strength = <MTK_DRIVE_8mA>; |
| 112 | + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; |
| 113 | + }; |
| 114 | + }; |
| 115 | +}; |
| 116 | + |
| 117 | +&wifi { |
| 118 | + mediatek,mtd-eeprom = <&factory 0x0>; |
| 119 | +}; |
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