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Instruction_formats
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Instruction_formats
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Notes on the AVR (8-bit) instruction formats.
0000 0001 dddd rrrr movw (d,r >>1); Rd = Rr; Rd+1 = Rr+1
0000 0010 dddd rrrr muls ( signed: R1:R0 = Rdhi * Rrhi)
0000 0011 0ddd 0rrr mulsu ( mixed: R1:R0 = Rd_s_24+ * Rr_u_24+)
0000 0011 0ddd 1rrr fmul ( unsigned: R1:R0 = Rd_24+ * Rr_24+)
0000 0011 1ddd 0rrr fmuls ( signed: R1:R0 = Rd_24+ * Rr_24+)
0000 0011 1ddd 1rrr fmulsu ( mixed: R1:R0 = Rd_s_24+ * Rr_u_24+)
0000 01rd dddd rrrr cpc ( compare with carry) Rd - Rr - C
0000 10rd dddd rrrr sbc ( subtract with carry) Rd = Rd - Rr - C
0000 11rd dddd rrrr add ( add) Rd = Rd + Rr
0001 00rd dddd rrrr cpse ( compare, skip if equal)
0001 01rd dddd rrrr cp ( compare)
0001 10rd dddd rrrr sub
0001 11rd dddd rrrr adc
0010 00rd dddd rrrr and
0010 01rd dddd rrrr eor
0010 10rd dddd rrrr or
0010 11rd dddd rrrr mov
( Note: no addi, adci, or eori.)
0011 kkkk dddd kkkk cpi ( compare immediate)
0100 kkkk dddd kkkk sbci ( subtract with carry immediate)
0101 kkkk dddd kkkk subi ( subtract immediate)
0110 kkkk dddd kkkk ori
0111 kkkk dddd kkkk andi
1000 *See 10q0 ld/st z+q/y+q below
( In all ld/store or pop/push, s=0 means ld/pop, s=1 means st/push)
1001 00sd dddd 0000 lds/sts ( with following offset) ( 32-bit version) ( 2 cycle)
1001 00sd dddd 0001 ld/st z+
1001 00sd dddd 0010 ld/st -z
1001 00sd dddd 0011 *unimplemented*
1001 000d dddd 0100 lpm z ( Note: NO stm!!)
1001 000d dddd 0101 lpm z+ ( Note: NO stm!!)
1001 00sd dddd 0110 *unimplemented*
1001 00sd dddd 0111 *unimplemented*
1001 00sd dddd 1000 *unimplemented*
1001 00sd dddd 1001 ld/st y+
1001 00sd dddd 1010 ld/st -y
1001 00sd dddd 1011 *unimplemented*
1001 00sd dddd 1100 ld/st x
1001 00sd dddd 1101 ld/st x+
1001 00sd dddd 1110 ld/st -x
1001 00sd dddd 1111 push/pop Rd ( s=0 pop, s=1 push)
1001 010d dddd 0000 com
1001 010d dddd 0001 neg
1001 010d dddd 0010 swap ( swap nybbles)
1001 010d dddd 0011 inc
1001 010d dddd 0100 *unimplemented*
1001 010d dddd 0101 asr
1001 010d dddd 0110 lsr
1001 010d dddd 0111 ror
1001 0100 0sss 1000 bset ( set bit sss in SREG)
1001 0100 1sss 1000 bclr ( clear bit sss in SREG)
1001 0100 0000 1001 ijmp ( jump to Z)
1001 0101 0000 1001 icall ( call to Z)
1001 0101 0000 1000 ret
1001 0101 0001 1000 reti
1001 0101 1000 1000 sleep
1001 0101 1010 1000 wdr ( watchdog reset)
1001 0101 1100 1000 lpm ( R0 implied; R0 = Flash[Z])
1001 0101 1110 1000 spm ( ?? this doesn't make sense)
1001 0101 1111 1000 spm ( ?? this doesn't make sense)
1001 010d dddd 1010 dec
1001 010d dddd 1011 *unimplemented*
1001 010k kkkk 110k jmp ( long; 2nd word follows)
1001 010k kkkk 111k call ( long; 2nd word follows)
1001 0110 kkdd kkkk adiw ( add immed word; dd = reg pair; k = konst)
1001 0111 kkdd kkkk sbiw ( sub immed word; dd = reg pair; k = konst)
1001 1000 aaaa abbb cbi ( clear bit bbb in IO[a])
1001 1001 aaaa abbb sbic ( skip if bit bbb in IO[a] clear)
1001 1010 aaaa abbb sbi ( set bit bbb in IO[a])
1001 1011 aaaa abbb sbis ( skip if bit bbb in IO[a] set)
1001 11rd dddd rrrr mul ( unsigned: R1:R0 = Rd * Rr)
( In all ld/store or pop/push, s=0 means ld/pop, s=1 means st/push)
10q0 qqsd dddd 0qqq ld/st z+q
10q0 qqsd dddd 1qqq ld/st y+q
( Conflict with above!! What gives?)
( These are 1 cycle instructions; datasheet for 48/88/168 says lds and sts are
2 cycle, so they must be the 32-bit versions.)
1010 skkk dddd kkkk lds/sts ( store Rd to data space, 0 to 127) ( 16-bit versions)
1011 0aad dddd aaaa in ( Rd = IO[a])
1011 1aad dddd aaaa out ( IO[a] = Rd)
1100 kkkk kkkk kkkk rjmp ( relative)
1101 kkkk kkkk kkkk rcall ( relative)
1110 kkkk dddd kkkk ldi ( load immediate)
1111 00kk kkkk ksss brbs ( branch if bit sss set in SREG)
1111 01kk kkkk ksss brbc ( branch if bit sss clr in SREG)
1111 100d dddd 0bbb bld ( load bit from SREG T; Rd(bit b) = T)
1111 101d dddd 0bbb bst ( store bit to SREG T; T = Rd(bit b)
1111 110d dddd 0bbb sbrc ( skip if bit b in Rd clear)
1111 111d dddd 0bbb sbrs ( skip if bit b in Rd set)