forked from pciutils/pciutils
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathls-ecaps.c
1566 lines (1356 loc) · 45.6 KB
/
ls-ecaps.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* The PCI Utilities -- Show Extended Capabilities
*
* Copyright (c) 1997--2022 Martin Mares <mj@ucw.cz>
*
* Can be freely distributed and used under the terms of the GNU GPL.
*/
#include <stdio.h>
#include <string.h>
#include "lspci.h"
static void
cap_tph(struct device *d, int where)
{
u32 tph_cap;
printf("Transaction Processing Hints\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
return;
tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
if (tph_cap & PCI_TPH_INTVEC_SUP)
printf("\t\tInterrupt vector mode supported\n");
if (tph_cap & PCI_TPH_DEV_SUP)
printf("\t\tDevice specific mode supported\n");
if (tph_cap & PCI_TPH_EXT_REQ_SUP)
printf("\t\tExtended requester support\n");
switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
case PCI_TPH_ST_NONE:
printf("\t\tNo steering table available\n");
break;
case PCI_TPH_ST_CAP:
printf("\t\tSteering table in TPH capability structure\n");
break;
case PCI_TPH_ST_MSIX:
printf("\t\tSteering table in MSI-X table\n");
break;
default:
printf("\t\tReserved steering table location\n");
break;
}
}
static u32
cap_ltr_scale(u8 scale)
{
return 1 << (scale * 5);
}
static void
cap_ltr(struct device *d, int where)
{
u32 scale;
u16 snoop, nosnoop;
printf("Latency Tolerance Reporting\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
return;
snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
printf("\t\tMax snoop latency: %" PCI_U64_FMT_U "ns\n",
((u64)snoop & PCI_LTR_VALUE_MASK) * scale);
nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
printf("\t\tMax no snoop latency: %" PCI_U64_FMT_U "ns\n",
((u64)nosnoop & PCI_LTR_VALUE_MASK) * scale);
}
static void
cap_sec(struct device *d, int where)
{
u32 ctrl3, lane_err_stat;
u8 lane;
printf("Secondary PCI Express\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + PCI_SEC_LNKCTL3, 12))
return;
ctrl3 = get_conf_word(d, where + PCI_SEC_LNKCTL3);
printf("\t\tLnkCtl3: LnkEquIntrruptEn%c PerformEqu%c\n",
FLAG(ctrl3, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN),
FLAG(ctrl3, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU));
lane_err_stat = get_conf_word(d, where + PCI_SEC_LANE_ERR);
printf("\t\tLaneErrStat: ");
if (lane_err_stat)
{
printf("LaneErr at lane:");
for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1)
if (BITS(lane_err_stat, 0, 1))
printf(" %u", lane);
}
else
printf("0");
printf("\n");
}
static void
cap_dsn(struct device *d, int where)
{
u32 t1, t2;
if (!config_fetch(d, where + 4, 8))
return;
t1 = get_conf_long(d, where + 4);
t2 = get_conf_long(d, where + 8);
printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
}
static void
cap_aer(struct device *d, int where, int type)
{
u32 l, l0, l1, l2, l3;
u16 w;
printf("Advanced Error Reporting\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40))
return;
l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
"MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
"MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
"MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
l = get_conf_long(d, where + PCI_ERR_COR_MASK);
printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
l = get_conf_long(d, where + PCI_ERR_CAP);
printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
"\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE),
FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG));
l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG);
l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4);
l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8);
l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12);
printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3);
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
{
if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12))
return;
l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND);
printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n",
FLAG(l, PCI_ERR_ROOT_CMD_COR_EN),
FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN),
FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN));
l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS);
printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
"\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n",
FLAG(l, PCI_ERR_ROOT_COR_RCV),
FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV),
FLAG(l, PCI_ERR_ROOT_UNCOR_RCV),
FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV),
FLAG(l, PCI_ERR_ROOT_FIRST_FATAL),
FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV),
FLAG(l, PCI_ERR_ROOT_FATAL_RCV),
PCI_ERR_MSG_NUM(l));
w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC);
printf("\t\tErrorSrc: ERR_COR: %04x ", w);
w = get_conf_word(d, where + PCI_ERR_ROOT_SRC);
printf("ERR_FATAL/NONFATAL: %04x\n", w);
}
}
static void cap_dpc(struct device *d, int where)
{
u16 l;
printf("Downstream Port Containment\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + PCI_DPC_CAP, 8))
return;
l = get_conf_word(d, where + PCI_DPC_CAP);
printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
l = get_conf_word(d, where + PCI_DPC_CTL);
printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),
FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),
FLAG(l, PCI_DPC_CTL_DL_ACTIVE));
l = get_conf_word(d, where + PCI_DPC_STATUS);
printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),
FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));
l = get_conf_word(d, where + PCI_DPC_SOURCE);
printf("\t\tSource:\t%04x\n", l);
}
static void
cap_acs(struct device *d, int where)
{
u16 w;
printf("Access Control Services\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + PCI_ACS_CAP, 4))
return;
w = get_conf_word(d, where + PCI_ACS_CAP);
printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
"DirectTrans%c\n",
FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
FLAG(w, PCI_ACS_CAP_TRANS));
w = get_conf_word(d, where + PCI_ACS_CTRL);
printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
"DirectTrans%c\n",
FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
FLAG(w, PCI_ACS_CTRL_TRANS));
}
static void
cap_ari(struct device *d, int where)
{
u16 w;
printf("Alternative Routing-ID Interpretation (ARI)\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + PCI_ARI_CAP, 4))
return;
w = get_conf_word(d, where + PCI_ARI_CAP);
printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
PCI_ARI_CAP_NFN(w));
w = get_conf_word(d, where + PCI_ARI_CTRL);
printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
PCI_ARI_CTRL_FG(w));
}
static void
cap_ats(struct device *d, int where)
{
u16 w;
printf("Address Translation Service (ATS)\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + PCI_ATS_CAP, 4))
return;
w = get_conf_word(d, where + PCI_ATS_CAP);
printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
w = get_conf_word(d, where + PCI_ATS_CTRL);
printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
}
static void
cap_pri(struct device *d, int where)
{
u16 w;
u32 l;
printf("Page Request Interface (PRI)\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc))
return;
w = get_conf_word(d, where + PCI_PRI_CTRL);
printf("\t\tPRICtl: Enable%c Reset%c\n",
FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
w = get_conf_word(d, where + PCI_PRI_STATUS);
printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
FLAG(w, PCI_PRI_STATUS_STOPPED));
l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
printf("\t\tPage Request Capacity: %08x, ", l);
l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
printf("Page Request Allocation: %08x\n", l);
}
static void
cap_pasid(struct device *d, int where)
{
u16 w;
printf("Process Address Space ID (PASID)\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + PCI_PASID_CAP, 4))
return;
w = get_conf_word(d, where + PCI_PASID_CAP);
printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV),
PCI_PASID_CAP_WIDTH(w));
w = get_conf_word(d, where + PCI_PASID_CTRL);
printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC),
FLAG(w, PCI_PASID_CTRL_PRIV));
}
static void
cap_sriov(struct device *d, int where)
{
u16 b;
u16 w;
u32 l;
int i;
printf("Single Root I/O Virtualization (SR-IOV)\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
return;
l = get_conf_long(d, where + PCI_IOV_CAP);
printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c Interrupt Message Number: %03x\n",
FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l));
w = get_conf_word(d, where + PCI_IOV_CTRL);
printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n",
FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
FLAG(w, PCI_IOV_CTRL_ARI), FLAG(w, PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN));
w = get_conf_word(d, where + PCI_IOV_STATUS);
printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
w = get_conf_word(d, where + PCI_IOV_INITIALVF);
printf("\t\tInitial VFs: %d, ", w);
w = get_conf_word(d, where + PCI_IOV_TOTALVF);
printf("Total VFs: %d, ", w);
w = get_conf_word(d, where + PCI_IOV_NUMVF);
printf("Number of VFs: %d, ", w);
b = get_conf_byte(d, where + PCI_IOV_FDL);
printf("Function Dependency Link: %02x\n", b);
w = get_conf_word(d, where + PCI_IOV_OFFSET);
printf("\t\tVF offset: %d, ", w);
w = get_conf_word(d, where + PCI_IOV_STRIDE);
printf("stride: %d, ", w);
w = get_conf_word(d, where + PCI_IOV_DID);
printf("Device ID: %04x\n", w);
l = get_conf_long(d, where + PCI_IOV_SUPPS);
printf("\t\tSupported Page Size: %08x, ", l);
l = get_conf_long(d, where + PCI_IOV_SYSPS);
printf("System Page Size: %08x\n", l);
for (i=0; i < PCI_IOV_NUM_BAR; i++)
{
u32 addr;
int type;
u32 h;
l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
if (l == 0xffffffff)
l = 0;
if (!l)
continue;
printf("\t\tRegion %d: Memory at ", i);
addr = l & PCI_ADDR_MEM_MASK;
type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
{
i++;
h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
printf("%08x", h);
}
printf("%08x (%s-bit, %sprefetchable)\n",
addr,
(type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
(l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
}
l = get_conf_long(d, where + PCI_IOV_MSAO);
printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
PCI_IOV_MSA_BIR(l));
}
static void
cap_multicast(struct device *d, int where, int type)
{
u16 w;
u32 l;
u64 bar, rcv, block;
printf("Multicast\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30))
return;
w = get_conf_word(d, where + PCI_MCAST_CAP);
printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1);
if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
printf(", WindowSz %d (%d bytes)",
PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w));
if (type == PCI_EXP_TYPE_ROOT_PORT ||
type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM)
printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC));
w = get_conf_word(d, where + PCI_MCAST_CTRL);
printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE));
bar = get_conf_long(d, where + PCI_MCAST_BAR);
l = get_conf_long(d, where + PCI_MCAST_BAR + 4);
bar |= (u64) l << 32;
printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n",
PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK);
rcv = get_conf_long(d, where + PCI_MCAST_RCV);
l = get_conf_long(d, where + PCI_MCAST_RCV + 4);
rcv |= (u64) l << 32;
printf("\t\tMcastReceiveVec: %016" PCI_U64_FMT_X "\n", rcv);
block = get_conf_long(d, where + PCI_MCAST_BLOCK);
l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4);
block |= (u64) l << 32;
printf("\t\tMcastBlockAllVec: %016" PCI_U64_FMT_X "\n", block);
block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS);
l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4);
block |= (u64) l << 32;
printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block);
if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
return;
bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR);
l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4);
bar |= (u64) l << 32;
printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar));
if (PCI_MCAST_OVL_SIZE(bar) >= 6)
printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar));
else
printf("(disabled)");
printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK);
}
static void
cap_vc(struct device *d, int where)
{
u32 cr1, cr2;
u16 ctrl, status;
int evc_cnt;
int arb_table_pos;
int i, j;
static const char ref_clocks[][6] = { "100ns" };
static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
char buf[8];
printf("Virtual Channel\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + 4, 0x1c - 4))
return;
cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
evc_cnt = BITS(cr1, 0, 3);
printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
BITS(cr1, 4, 3),
TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
1 << BITS(cr1, 10, 2));
printf("\t\tArb:");
for (i=0; i<8; i++)
if (arb_selects[i][0] != '?' || cr2 & (1 << i))
printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
arb_table_pos = BITS(cr2, 24, 8);
printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
if (arb_table_pos)
{
arb_table_pos = where + 16*arb_table_pos;
printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
}
for (i=0; i<=evc_cnt; i++)
{
int pos = where + PCI_VC_RES_CAP + 12*i;
u32 rcap, rctrl;
u16 rstatus;
int pat_pos;
printf("\t\tVC%d:\t", i);
if (!config_fetch(d, pos, 12))
{
printf("<unreadable>\n");
continue;
}
rcap = get_conf_long(d, pos);
rctrl = get_conf_long(d, pos+4);
rstatus = get_conf_word(d, pos+10);
pat_pos = BITS(rcap, 24, 8);
printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
pat_pos,
BITS(rcap, 16, 7) + 1,
FLAG(rcap, 1 << 15));
printf("\t\t\tArb:");
for (j=0; j<8; j++)
if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
FLAG(rctrl, 1 << 31),
BITS(rctrl, 24, 3),
TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
BITS(rctrl, 0, 8));
printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
FLAG(rstatus, 2),
FLAG(rstatus, 1));
if (pat_pos)
printf("\t\t\tPort Arbitration Table <?>\n");
}
}
static void
cap_rclink(struct device *d, int where)
{
u32 esd;
int num_links;
int i;
static const char elt_types[][9] = { "Config", "Egress", "Internal" };
char buf[8];
printf("Root Complex Link\n");
if (verbose < 2)
return;
if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
return;
esd = get_conf_long(d, where + PCI_RCLINK_ESD);
num_links = BITS(esd, 8, 8);
printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
BITS(esd, 24, 8),
BITS(esd, 16, 8),
TABLE(elt_types, BITS(esd, 0, 8), buf));
for (i=0; i<num_links; i++)
{
int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
u32 desc;
u32 addr_lo, addr_hi;
printf("\t\tLink%d:\t", i);
if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
{
printf("<unreadable>\n");
return;
}
desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
BITS(desc, 24, 8),
BITS(desc, 16, 8),
FLAG(desc, 4),
((desc & 2) ? "Config" : "MemMapped"),
FLAG(desc, 1));
if (desc & 2)
{
int n = addr_lo & 7;
if (!n)
n = 8;
printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
BITS(addr_lo, 20, n),
BITS(addr_lo, 15, 5),
BITS(addr_lo, 12, 3),
addr_hi, addr_lo);
}
else
printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
}
}
static void
cap_rcec(struct device *d, int where)
{
printf("Root Complex Event Collector Endpoint Association\n");
if (verbose < 2)
return;
if (!config_fetch(d, where, 12))
return;
u32 hdr = get_conf_long(d, where);
byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr);
u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP);
printf("\t\tRCiEPBitmap: ");
if (bmap)
{
int prevmatched=0;
int adjcount=0;
int prevdev=0;
printf("RCiEP at Device(s):");
for (int dev=0; dev < 32; dev++)
{
if (BITS(bmap, dev, 1))
{
if (!adjcount)
printf("%s %u", (prevmatched) ? "," : "", dev);
adjcount++;
prevdev=dev;
prevmatched=1;
}
else
{
if (adjcount > 1)
printf("-%u", prevdev);
adjcount=0;
}
}
}
else
printf("%s", (verbose > 2) ? "00000000 [none]" : "[none]");
printf("\n");
if (cap_ver < PCI_RCEC_BUSN_REG_VER)
return;
u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG);
u8 lastbusn = BITS(busn, 16, 8);
u8 nextbusn = BITS(busn, 8, 8);
if ((lastbusn == 0x00) && (nextbusn == 0xff))
printf("\t\tAssociatedBusNumbers: %s\n", (verbose > 2) ? "ff-00 [none]" : "[none]");
else
printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn );
}
static void
cxl_range(u64 base, u64 size, int n)
{
u32 interleave[] = { 0, 256, 4096, 512, 1024, 2048, 8192, 16384 };
const char *type[] = { "Volatile", "Non-volatile", "CDAT" };
const char *class[] = { "DRAM", "Storage", "CDAT" };
u16 w;
w = (u16) size;
size &= ~0x0fffffffULL;
printf("\t\tRange%d: %016"PCI_U64_FMT_X"-%016"PCI_U64_FMT_X"\n", n, base, base + size - 1);
printf("\t\t\tValid%c Active%c Type=%s Class=%s interleave=%d timeout=%ds\n",
FLAG(w, PCI_CXL_RANGE_VALID), FLAG(w, PCI_CXL_RANGE_ACTIVE),
type[PCI_CXL_RANGE_TYPE(w)], class[PCI_CXL_RANGE_CLASS(w)],
interleave[PCI_CXL_RANGE_INTERLEAVE(w)],
1 << (PCI_CXL_RANGE_TIMEOUT(w) * 2));
}
static void
dvsec_cxl_device(struct device *d, int rev, int where, int len)
{
u32 cache_size, cache_unit_size;
u64 range_base, range_size;
u16 w;
if (len < PCI_CXL_DEV_LEN)
return;
/* Legacy 1.1 revs aren't handled */
if (rev < 1)
return;
w = get_conf_word(d, where + PCI_CXL_DEV_CAP);
printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n",
FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM),
FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL));
w = get_conf_word(d, where + PCI_CXL_DEV_CTRL);
printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n",
FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM),
PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN),
FLAG(w, PCI_CXL_DEV_CTRL_VIRAL));
w = get_conf_word(d, where + PCI_CXL_DEV_STATUS);
printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL));
w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2);
printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n",
FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC));
w = get_conf_word(d, where + PCI_CXL_DEV_CAP2);
cache_unit_size = BITS(w, 0, 4);
cache_size = BITS(w, 8, 8);
switch (cache_unit_size)
{
case PCI_CXL_DEV_CAP2_CACHE_1M:
printf("\t\tCache Size: %08x\n", cache_size * (1<<20));
break;
case PCI_CXL_DEV_CAP2_CACHE_64K:
printf("\t\tCache Size: %08x\n", cache_size * (64<<10));
break;
case PCI_CXL_DEV_CAP2_CACHE_UNK:
printf("\t\tCache Size Not Reported\n");
break;
default:
printf("\t\tCache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size);
break;
}
range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32;
range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32;
range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
cxl_range(range_base, range_size, 1);
range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32;
range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32;
range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
cxl_range(range_base, range_size, 2);
}
static void
dvsec_cxl_port(struct device *d, int where, int len)
{
u16 w, m1, m2;
u8 b1, b2;
if (len < PCI_CXL_PORT_EXT_LEN)
return;
w = get_conf_word(d, where + PCI_CXL_PORT_EXT_STATUS);
printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS));
w = get_conf_word(d, where + PCI_CXL_PORT_CTRL);
printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c ViralEnable%c\n",
FLAG(w, PCI_CXL_PORT_UNMASK_SBR), FLAG(w, PCI_CXL_PORT_UNMASK_LINK),
FLAG(w, PCI_CXL_PORT_ALT_MEMORY), FLAG(w, PCI_CXL_PORT_ALT_BME),
FLAG(w, PCI_CXL_PORT_VIRAL_EN));
b1 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_BASE);
b2 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_LIMIT);
printf("\t\tAlternateBus:\t%02x-%02x\n", b1, b2);
m1 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_BASE);
m2 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_LIMIT);
printf("\t\tAlternateBus:\t%04x-%04x\n", m1, m2);
}
static void
dvsec_cxl_register_locator(struct device *d, int where, int len)
{
static const char * const id_names[] = {
"empty",
"component registers",
"BAR virtualization",
"CXL device registers",
"CPMU registers",
};
for (int i=0; ; i++)
{
int pos = where + PCI_CXL_RL_BLOCK1_LO + 8*i;
if (pos + 7 >= where + len)
break;
u32 lo = get_conf_long(d, pos);
u32 hi = get_conf_long(d, pos + 4);
unsigned int bir = BITS(lo, 0, 3);
unsigned int block_id = BITS(lo, 8, 8);
u64 base = (BITS(lo, 16, 16) << 16) | ((u64) hi << 32);
if (!block_id)
continue;
const char *id_name;
if (block_id < sizeof(id_names) / sizeof(*id_names))
id_name = id_names[block_id];
else if (block_id == 0xff)
id_name = "vendor-specific";
else
id_name = "<?>";
printf("\t\tBlock%d: BIR: bar%d, ID: %s, offset: %016" PCI_U64_FMT_X "\n", i + 1, bir, id_name, base);
}
}
static void
dvsec_cxl_gpf_device(struct device *d, int where)
{
u32 l;
u16 w, duration;
u8 time_base, time_scale;
w = get_conf_word(d, where + PCI_CXL_GPF_DEV_PHASE2_DUR);
time_base = BITS(w, 0, 4);
time_scale = BITS(w, 8, 4);
switch (time_scale)
{
case PCI_CXL_GPF_DEV_100US:
case PCI_CXL_GPF_DEV_100MS:
duration = time_base * 100;
break;
case PCI_CXL_GPF_DEV_10US:
case PCI_CXL_GPF_DEV_10MS:
case PCI_CXL_GPF_DEV_10S:
duration = time_base * 10;
break;
case PCI_CXL_GPF_DEV_1US:
case PCI_CXL_GPF_DEV_1MS:
case PCI_CXL_GPF_DEV_1S:
duration = time_base;
break;
default:
/* Reserved */
printf("\t\tReserved time scale encoding %x\n", time_scale);
duration = time_base;
}
printf("\t\tGPF Phase 2 Duration: %u%s\n", duration,
(time_scale < PCI_CXL_GPF_DEV_1MS) ? "us":
(time_scale < PCI_CXL_GPF_DEV_1S) ? "ms" :
(time_scale == PCI_CXL_GPF_DEV_1S) ? "s" : "<?>");
l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW);
printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l);
}
static void
dvsec_cxl_gpf_port(struct device *d, int where)
{
u16 w, timeout;
u8 time_base, time_scale;
w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE1_CTRL);
time_base = BITS(w, 0, 4);
time_scale = BITS(w, 8, 4);
switch (time_scale)
{
case PCI_CXL_GPF_PORT_100US:
case PCI_CXL_GPF_PORT_100MS:
timeout = time_base * 100;
break;
case PCI_CXL_GPF_PORT_10US:
case PCI_CXL_GPF_PORT_10MS:
case PCI_CXL_GPF_PORT_10S:
timeout = time_base * 10;
break;
case PCI_CXL_GPF_PORT_1US:
case PCI_CXL_GPF_PORT_1MS:
case PCI_CXL_GPF_PORT_1S:
timeout = time_base;
break;
default:
/* Reserved */
printf("\t\tReserved time scale encoding %x\n", time_scale);
timeout = time_base;
}
printf("\t\tGPF Phase 1 Timeout: %d%s\n", timeout,
(time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
(time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
(time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE2_CTRL);
time_base = BITS(w, 0, 4);
time_scale = BITS(w, 8, 4);
switch (time_scale)
{
case PCI_CXL_GPF_PORT_100US:
case PCI_CXL_GPF_PORT_100MS:
timeout = time_base * 100;
break;
case PCI_CXL_GPF_PORT_10US:
case PCI_CXL_GPF_PORT_10MS:
case PCI_CXL_GPF_PORT_10S:
timeout = time_base * 10;
break;
case PCI_CXL_GPF_PORT_1US:
case PCI_CXL_GPF_PORT_1MS:
case PCI_CXL_GPF_PORT_1S:
timeout = time_base;
break;
default:
/* Reserved */
printf("\t\tReserved time scale encoding %x\n", time_scale);
timeout = time_base;
}
printf("\t\tGPF Phase 2 Timeout: %d%s\n", timeout,
(time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
(time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
(time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
}
static void
dvsec_cxl_flex_bus(struct device *d, int where, int rev)
{
u16 w;
u32 l, data;
if (rev < 1)
{
printf("\t\tRevision %d not supported\n", rev);
return;
}
w = get_conf_word(d, where + PCI_CXL_FB_PORT_CAP);
printf("\t\tFBCap:\tCache%c IO%c Mem%c 68BFlit%c MltLogDev%c",
FLAG(w, PCI_CXL_FB_CAP_CACHE), FLAG(w, PCI_CXL_FB_CAP_IO),
FLAG(w, PCI_CXL_FB_CAP_MEM), FLAG(w, PCI_CXL_FB_CAP_68B_FLIT),
FLAG(w, PCI_CXL_FB_CAP_MULT_LOG_DEV));
if (rev > 1)
printf(" 256BFlit%c PBRFlit%c",
FLAG(w, PCI_CXL_FB_CAP_256B_FLIT), FLAG(w, PCI_CXL_FB_CAP_PBR_FLIT));
w = get_conf_word(d, where + PCI_CXL_FB_PORT_CTRL);
printf("\n\t\tFBCtl:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c",
FLAG(w, PCI_CXL_FB_CTRL_CACHE), FLAG(w, PCI_CXL_FB_CTRL_IO),
FLAG(w, PCI_CXL_FB_CTRL_MEM), FLAG(w, PCI_CXL_FB_CTRL_SYNC_HDR_BYP),
FLAG(w, PCI_CXL_FB_CTRL_DRFT_BUF), FLAG(w, PCI_CXL_FB_CTRL_68B_FLIT),
FLAG(w, PCI_CXL_FB_CTRL_MULT_LOG_DEV), FLAG(w, PCI_CXL_FB_CTRL_RCD),
FLAG(w, PCI_CXL_FB_CTRL_RETIMER1), FLAG(w, PCI_CXL_FB_CTRL_RETIMER2));
if (rev > 1)
printf(" 256BFlit%c PBRFlit%c",
FLAG(w, PCI_CXL_FB_CTRL_256B_FLIT), FLAG(w, PCI_CXL_FB_CTRL_PBR_FLIT));
w = get_conf_word(d, where + PCI_CXL_FB_PORT_STATUS);
printf("\n\t\tFBSta:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c",
FLAG(w, PCI_CXL_FB_STAT_CACHE), FLAG(w, PCI_CXL_FB_STAT_IO),
FLAG(w, PCI_CXL_FB_STAT_MEM), FLAG(w, PCI_CXL_FB_STAT_SYNC_HDR_BYP),
FLAG(w, PCI_CXL_FB_STAT_DRFT_BUF), FLAG(w, PCI_CXL_FB_STAT_68B_FLIT),
FLAG(w, PCI_CXL_FB_STAT_MULT_LOG_DEV));
if (rev > 1)
printf(" 256BFlit%c PBRFlit%c",
FLAG(w, PCI_CXL_FB_STAT_256B_FLIT), FLAG(w, PCI_CXL_FB_STAT_PBR_FLIT));
l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA);
data = BITS(l, 0, 24);
printf("\n\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data);