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kapi-nokapi-no
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applications: nrf_desktop: nrf54h20: migrate to ironside se
Updated the nrf54h20dk/nrf54h20/cpuapp and nrf54h20dk/nrf54h20/cpurad board target configurations in the nRF Desktop application to align them with the new nRF54H20 SW architecture that is based on the IronSide SE. Added the MCUboot bootloader configuration and replaced the default nRF54H20 partition map with the custom application-optimized memory map. The updated configuration is the first step towards the complete feature migration. The following features are disabled and not yet supported: - MCUmgr DFU with the Bluetooth transport - Config Channel DFU with both the USB and Bluetooth transports - DVFS Ref: NCSDK-34151 Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
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‎applications/nrf_desktop/configuration/nrf54h20dk_nrf54h20_cpuapp/app_common.dtsi‎

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2024-2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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#include "memory_map.dtsi"
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/ {
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/* Redefine leds to fit CAF requirements. */
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/delete-node/ leds;
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label = "Green LED 3";
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};
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};
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aliases {
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nrfdesktop-dvfs-clock = &cpuapp_hsfll;
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};
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};
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&cpusec_cpuapp_ipc {
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status = "okay";
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/* Define the necessary aliases for the MCUboot slots that will be used by the DFU transports.
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* Due to the build system limitation, the allowed size of the application image (configured by
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* the code partition DTS node) is incorrectly increased by the size allocated for the radio image.
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*/
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slot0_partition: &cpuapp_slot0_partition {
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label = "image-0";
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};
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&cpusec_bellboard {
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status = "okay";
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slot1_partition: &cpuapp_slot1_partition {
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label = "image-1";
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};
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/* Shrink ppr partition as ppr core is not used and extend app core code partition. */
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&cpuppr_code_partition {
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reg = < 0xf8000 DT_SIZE_K(32) >;
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/* Remove the undefined property value from the disabled VPR cores to prevent build errors. */
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&cpuflpr_vpr {
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/delete-property/ source-memory;
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};
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&cpuapp_slot0_partition {
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reg = < 0xa6000 DT_SIZE_K(328) >;
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&cpuppr_vpr {
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/delete-property/ source-memory;
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};

‎applications/nrf_desktop/configuration/nrf54h20dk_nrf54h20_cpuapp/images/mcuboot/app.overlay‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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#include "../../memory_map.dtsi"
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/* The nRF54H20 DK defines memory map using DTS.
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* Assign the bootloader partition to the MCUboot image.
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*/
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/ {
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chosen {
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zephyr,code-partition = &cpuapp_boot_partition;
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};
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};
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/* Define the necessary aliases for the DTS partition nodes that contain the application and
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* radio images.
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*/
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slot0_partition: &cpuapp_slot0_partition {
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label = "image-0";
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};
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slot1_partition: &cpuapp_slot1_partition {
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label = "image-1";
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};
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/* Remove the undefined property value from the disabled VPR cores to prevent build errors. */
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&cpuflpr_vpr {
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/delete-property/ source-memory;
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};
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&cpuppr_vpr {
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/delete-property/ source-memory;
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};

‎applications/nrf_desktop/configuration/nrf54h20dk_nrf54h20_cpuapp/images/mcuboot/mcuboot_private.pem‎

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-----BEGIN PRIVATE KEY-----
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MC4CAQAwBQYDK2VwBCIEIFe3odXpEgmHpGsRmLZkC9FS+DMxKO5yi6BmKTctX05/
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-----END PRIVATE KEY-----

‎applications/nrf_desktop/configuration/nrf54h20dk_nrf54h20_cpuapp/images/mcuboot/prj.conf‎

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#
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# Copyright (c) 2025 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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CONFIG_SIZE_OPTIMIZATIONS=y
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CONFIG_HW_STACK_PROTECTION=y
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CONFIG_MAIN_STACK_SIZE=10240
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CONFIG_BOOT_BOOTSTRAP=n
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CONFIG_BOOT_VERSION_CMP_USE_BUILD_NUMBER=y
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CONFIG_FLASH=y
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# CONFIG_FPROTECT is not supported yet on the nRF54H20 SoC
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# Configure Zephyr system power management
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# The Zephyr system power management is used by the MCUboot bootloader to detect wake-up from
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# S2RAM and redirect execution to the resume routine of the application image
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CONFIG_PM=y
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CONFIG_PM_S2RAM=y
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CONFIG_PM_S2RAM_CUSTOM_MARKING=y
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# Enable HW cryptography in the MCUboot bootloader and its dependencies
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# The PSA operations are handled by the SDFW Service Framework (SDFW)
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# that is enabled with the CONFIG_PSA_SSF_CRYPTO_CLIENT Kconfig option.
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CONFIG_NRF_SECURITY=y
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CONFIG_MULTITHREADING=y
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CONFIG_PSA_SSF_CRYPTO_CLIENT=y
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# Reduce memory consumption
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CONFIG_BOOT_BANNER=n
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CONFIG_NCS_BOOT_BANNER=n
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CONFIG_CLOCK_CONTROL=n
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CONFIG_SPI_NOR=n
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CONFIG_GPIO=n
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CONFIG_SERIAL=n
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CONFIG_CONSOLE=n
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CONFIG_UART_CONSOLE=n
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CONFIG_PRINTK=n
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CONFIG_USE_SEGGER_RTT=n
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# Use minimal C library instead of the Picolib
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CONFIG_MINIMAL_LIBC=y
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# Activate Link Time Optimization (LTO)
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CONFIG_LTO=y
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CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
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# Improve debugging experience by disabling reset on fatal error
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CONFIG_RESET_ON_FATAL_ERROR=n

‎applications/nrf_desktop/configuration/nrf54h20dk_nrf54h20_cpuapp/images/mcuboot/prj_dongle.conf‎

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#
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# Copyright (c) 2025 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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CONFIG_SIZE_OPTIMIZATIONS=y
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CONFIG_HW_STACK_PROTECTION=y
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CONFIG_MAIN_STACK_SIZE=10240
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CONFIG_BOOT_BOOTSTRAP=n
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CONFIG_BOOT_VERSION_CMP_USE_BUILD_NUMBER=y
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CONFIG_FLASH=y
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# CONFIG_FPROTECT is not supported yet on the nRF54H20 SoC
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# Configure Zephyr system power management
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# The Zephyr system power management is used by the MCUboot bootloader to detect wake-up from
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# S2RAM and redirect execution to the resume routine of the application image
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CONFIG_PM=y
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CONFIG_PM_S2RAM=y
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CONFIG_PM_S2RAM_CUSTOM_MARKING=y
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# Enable HW cryptography in the MCUboot bootloader and its dependencies
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# The PSA operations are handled by the SDFW Service Framework (SDFW)
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# that is enabled with the CONFIG_PSA_SSF_CRYPTO_CLIENT Kconfig option.
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CONFIG_NRF_SECURITY=y
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CONFIG_MULTITHREADING=y
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CONFIG_PSA_SSF_CRYPTO_CLIENT=y
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# Reduce memory consumption
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CONFIG_BOOT_BANNER=n
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CONFIG_NCS_BOOT_BANNER=n
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CONFIG_CLOCK_CONTROL=n
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CONFIG_SPI_NOR=n
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CONFIG_GPIO=n
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CONFIG_SERIAL=n
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CONFIG_CONSOLE=n
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CONFIG_UART_CONSOLE=n
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CONFIG_PRINTK=n
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CONFIG_USE_SEGGER_RTT=n
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# Use minimal C library instead of the Picolib
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CONFIG_MINIMAL_LIBC=y
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# Activate Link Time Optimization (LTO)
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CONFIG_LTO=y
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CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
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# Improve debugging experience by disabling reset on fatal error
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CONFIG_RESET_ON_FATAL_ERROR=n

‎applications/nrf_desktop/configuration/nrf54h20dk_nrf54h20_cpuapp/images/mcuboot/prj_release.conf‎

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#
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# Copyright (c) 2025 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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CONFIG_SIZE_OPTIMIZATIONS=y
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CONFIG_HW_STACK_PROTECTION=y
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CONFIG_MAIN_STACK_SIZE=10240
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CONFIG_BOOT_BOOTSTRAP=n
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CONFIG_BOOT_VERSION_CMP_USE_BUILD_NUMBER=y
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CONFIG_FLASH=y
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# CONFIG_FPROTECT is not supported yet on the nRF54H20 SoC
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CONFIG_RESET_ON_FATAL_ERROR=y
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# Configure Zephyr system power management
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# The Zephyr system power management is used by the MCUboot bootloader to detect wake-up from
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# S2RAM and redirect execution to the resume routine of the application image
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CONFIG_PM=y
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CONFIG_PM_S2RAM=y
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CONFIG_PM_S2RAM_CUSTOM_MARKING=y
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# Enable HW cryptography in the MCUboot bootloader and its dependencies
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# The PSA operations are handled by the SDFW Service Framework (SDFW)
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# that is enabled with the CONFIG_PSA_SSF_CRYPTO_CLIENT Kconfig option.
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CONFIG_NRF_SECURITY=y
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CONFIG_MULTITHREADING=y
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CONFIG_PSA_SSF_CRYPTO_CLIENT=y
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# Reduce memory consumption
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CONFIG_BOOT_BANNER=n
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CONFIG_NCS_BOOT_BANNER=n
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CONFIG_CLOCK_CONTROL=n
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CONFIG_SPI_NOR=n
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CONFIG_GPIO=n
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CONFIG_SERIAL=n
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CONFIG_CONSOLE=n
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CONFIG_UART_CONSOLE=n
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CONFIG_PRINTK=n
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CONFIG_USE_SEGGER_RTT=n
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# Use minimal C library instead of the Picolib
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CONFIG_MINIMAL_LIBC=y
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# Activate Link Time Optimization (LTO)
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CONFIG_LTO=y
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CONFIG_ISR_TABLES_LOCAL_DECLARATION=y

‎applications/nrf_desktop/configuration/nrf54h20dk_nrf54h20_cpuapp/images/mcuboot/prj_release_dongle.conf‎

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#
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# Copyright (c) 2025 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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CONFIG_SIZE_OPTIMIZATIONS=y
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CONFIG_HW_STACK_PROTECTION=y
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CONFIG_MAIN_STACK_SIZE=10240
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CONFIG_BOOT_BOOTSTRAP=n
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CONFIG_BOOT_VERSION_CMP_USE_BUILD_NUMBER=y
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CONFIG_FLASH=y
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# CONFIG_FPROTECT is not supported yet on the nRF54H20 SoC
16+
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CONFIG_RESET_ON_FATAL_ERROR=y
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# Configure Zephyr system power management
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# The Zephyr system power management is used by the MCUboot bootloader to detect wake-up from
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# S2RAM and redirect execution to the resume routine of the application image
22+
CONFIG_PM=y
23+
CONFIG_PM_S2RAM=y
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CONFIG_PM_S2RAM_CUSTOM_MARKING=y
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# Enable HW cryptography in the MCUboot bootloader and its dependencies
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# The PSA operations are handled by the SDFW Service Framework (SDFW)
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# that is enabled with the CONFIG_PSA_SSF_CRYPTO_CLIENT Kconfig option.
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CONFIG_NRF_SECURITY=y
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CONFIG_MULTITHREADING=y
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CONFIG_PSA_SSF_CRYPTO_CLIENT=y
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# Reduce memory consumption
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CONFIG_BOOT_BANNER=n
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CONFIG_NCS_BOOT_BANNER=n
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CONFIG_CLOCK_CONTROL=n
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CONFIG_SPI_NOR=n
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CONFIG_GPIO=n
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CONFIG_SERIAL=n
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CONFIG_CONSOLE=n
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CONFIG_UART_CONSOLE=n
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CONFIG_PRINTK=n
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CONFIG_USE_SEGGER_RTT=n
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# Use minimal C library instead of the Picolib
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CONFIG_MINIMAL_LIBC=y
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# Activate Link Time Optimization (LTO)
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CONFIG_LTO=y
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CONFIG_ISR_TABLES_LOCAL_DECLARATION=y

‎applications/nrf_desktop/configuration/nrf54h20dk_nrf54h20_cpuapp/memory_map.dtsi‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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&mram1x {
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/delete-node/ partitions;
9+
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/* Redefine the "partitions" DTS node. */
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Partitions belonging to the MRAM_10 memory block.
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* The start of the MRAM_10 memory is reserved for internal IronSide SE firmware.
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*/
19+
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cpuapp_boot_partition: partition@30000 {
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reg = <0x30000 DT_SIZE_K(24)>;
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};
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/* Due to the build system limitation, the allowed size of the application image (configured by
25+
* the code partition DTS node) is incorrectly increased by the size allocated for the radio image.
26+
*/
27+
cpuapp_slot0_partition: partition@36000 {
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reg = <0x36000 DT_SIZE_K(808)>;
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};
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cpurad_slot0_partition: partition@c9000 {
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reg = <0xc9000 DT_SIZE_K(220)>;
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};
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/* Partitions belonging to the MRAM_11 memory block. */
36+
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/* Due to the build system limitation, the allowed size of the application image (configured by
38+
* the code partition DTS node) is incorrectly increased by the size allocated for the radio image.
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*/
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cpuapp_slot1_partition: partition@100000 {
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reg = <0x100000 DT_SIZE_K(808)>;
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};
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cpurad_slot1_partition: partition@193000 {
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reg = <0x193000 DT_SIZE_K(220)>;
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};
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storage_partition: partition@1ca000 {
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reg = <0x1ca000 DT_SIZE_K(40)>;
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};
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periphconf_partition: partition@1d4000 {
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reg = <0x1d4000 DT_SIZE_K(8)>;
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};
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/* The end of the MRAM_11 memory is left unallocated. */
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};
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};

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