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Cédric Le Goater edited this page Jan 11, 2019
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Welcome to the qemu wiki!
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LPC controller
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GPIO Controller
- should be useful for debug.
- RX8900 INT line should be connected to GPIOJ0 for Witherspoon (This is needed if RTC alarms are used)
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Clock infrastructure
- Derive clock rates from strapping and SCU clock registers
- review proposal from Frederic KONRAD
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MBOX
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FSI
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NCSI support
- currently only a fake user mode network stack (slirp) backend.
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OCC model ?
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Devices
- ir35221
- dps310
- max31785a
- bmp280
- ucd90160
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Network FTGMAC100
- High Priority Transmit Queue
- Wake-On-LAN functions
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BT device (part of the LPC Controller)
- initial implementation done using the OpenIPMI simulator protocol for a virtual machine described in : https://github.com/cminyard/openipmi/blob/master/lanserv/README.vm
- use -chardev to connect a PowerNV QEMU machine.
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VUART Controller
- dummy implementation done, no register handling, just a serial backend.
- use -chardev for external connection
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SMC:
- DMA (rework current implementation with a private address space)
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SuperIO
- required For OpenPOWER systems to access the flash. Will change in P9.
- I2C
- DMA support (used by Aspeed SDK 4)
- SMC controller
- DMA support
- Network FTGMAC100
- new MDIO interface
- SuperIO
- Timer fixes
- pca955x (done)
- Witherspoon (done)
- FTGMAC100 IEEE 802.1Q VLAN support (done)
- Witherspoon
- ftgmac100 (done)
- slirp/ncsi (done)
- ADC (sent)
- tmp42{123} device model (done)
- target-arm: Add VBAR support to ARM1176 CPUs. (done)
- romulus machine (done)
- smc:
- boot from flash image (done)
- command mode (done)
- dummy bytes for fast read in command mode (done)
- watchdog (done)
- tmp42{123} device model (sent but not merged)
- rx8900 RTC (sent but not merged)
- smc: segment registers support
- smc: ast2500 support. two spi controllers.
- ast2500 SoC
- ast2500 evaluation board
- SDMC controller
- i2c controller
- scu controller
- smc controller
- timer controller
- interrupt controller
- ast2400 SoC
- palmetto-bmc machine