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Bender.yml
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Bender.yml
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# Copyright 2020 ETH Zurich
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
package:
name: riscv
dependencies:
fpnew: { git: "https://github.com/pulp-platform/fpnew.git", version: 0.6.1 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.16.4 }
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.1.1 }
sources:
include_dirs:
- rtl/include
files:
- rtl/include/cv32e40p_apu_core_pkg.sv
- rtl/include/cv32e40p_pkg.sv
- rtl/cv32e40p_alu.sv
- rtl/cv32e40p_alu_div.sv
- rtl/cv32e40p_aligner.sv
- rtl/cv32e40p_compressed_decoder.sv
- rtl/cv32e40p_controller.sv
- rtl/cv32e40p_cs_registers.sv
- rtl/cv32e40p_decoder.sv
- rtl/cv32e40p_int_controller.sv
- rtl/cv32e40p_ex_stage.sv
- rtl/cv32e40p_hwloop_controller.sv
- rtl/cv32e40p_hwloop_regs.sv
- rtl/cv32e40p_id_stage.sv
- rtl/cv32e40p_if_stage.sv
- rtl/cv32e40p_load_store_unit.sv
- rtl/cv32e40p_mult.sv
- rtl/cv32e40p_prefetch_buffer.sv
- rtl/cv32e40p_obi_interface.sv
- rtl/cv32e40p_core.sv
- rtl/cv32e40p_apu_disp.sv
- rtl/cv32e40p_fetch_fifo.sv
- rtl/cv32e40p_popcnt.sv
- rtl/cv32e40p_ff_one.sv
- rtl/cv32e40p_sleep_unit.sv
- target: asic
files:
- rtl/cv32e40p_register_file_latch.sv
- target: not(asic)
files:
- rtl/cv32e40p_register_file_ff.sv
- target: rtl
files:
- bhv/cv32e40p_sim_clock_gate.sv