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Table of Contents Introduction Licensing Implementation statistics Code Size

Introduction

The mor1kx is an OpenRISC 1000 (or1k) compliant CPU implementation which is written in synthesisable Verilog.

There's more documentation in AsciiDoc format in the doc/ path.

If you're looking for reference SoCs (System on Chips) which use the mor1kx, look no further than mor1kx-dev-env - basically ORPSoC which has been customised for mor1kx development. There's tutorials on the wiki there with details on how to get up and running with this thing.

Licensing

This work is intended to be open source, but because there are no obviously appropriate licenses to achieve copy left for hardware designs (ultimately what RTL code becomes in ASICs - it's less obvious what it becomes in FPGAs) it's licensed under the Open Hardware Description License which I (Julius) made up out of the Mozilla Public License 2.0.

I want a weak copy-left hardware so ASIC designers can collaborate with us without fear of having to divulge the proprietary portions of the chip, which a strong copy-left license would require. Getting something back is better than getting nothing back.

If you don't like it, my license lets you relicense this work under the GPLs (are you crazy?!) or the more considered CERN OHL.

Licensing rant over.

Implementation statistics

TODO!

Code Size

Out of interest, here is how much code there is. (Verilog is similar to C code in terms of comments and general rules, so we'll count as C code here.)

 http://cloc.sourceforge.net v 1.56  T=0.5 s (68.0 files/s, 30726.0 lines/s)
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 Language                     files          blank        comment           code
 -------------------------------------------------------------------------------
 C                               34           2035           2389          10939
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 SUM:                            34           2035           2389          10939

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