Repositories list

• riscv-opcodes

  Public
  RISC-V Opcodes

  Python

  •

  BSD 3-Clause "New" or "Revised" License

  •312•0•0•0•Updated Feb 1, 2025Feb 1, 2025

• verilator

  Public
  Verilator open-source SystemVerilog simulator and lint system

  C++

  •

  GNU Lesser General Public License v3.0

  •633•0•0•0•Updated Dec 6, 2024Dec 6, 2024

• euvm

  Public
  Embedded UVM (D Language port of IEEE UVM 1.0)

  D

  •

  Apache License 2.0

  •14•31•11•0•Updated Aug 30, 2024Aug 30, 2024

• D-YAML

  Public
  YAML parser and emitter for the D programming language

  D

  •

  Boost Software License 1.0

  •39•0•0•0•Updated Jul 27, 2024Jul 27, 2024

• riscv-isa-sim

  Public
  Spike, a RISC-V ISA Simulator

  C

  •

  Other

  •900•0•0•0•Updated May 20, 2024May 20, 2024

• axi4reg

  Public
  AXI4 VIP for Reg Verifiation

  SystemVerilog

  •4•3•0•0•Updated Apr 29, 2024Apr 29, 2024

• ibex

  Public
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  SystemVerilog

  •

  Apache License 2.0

  •573•1•0•0•Updated Mar 22, 2024Mar 22, 2024

• riscv-dv

  Public
  Random instruction generator for RISC-V processor verification

  D

  •

  Apache License 2.0

  •333•2•0•4•Updated Feb 28, 2024Feb 28, 2024

• avst_adder_vl

  Public
  Reference eUVM testbench for verilator

  D

  •12•0•0•0•Updated Nov 27, 2023Nov 27, 2023

• PeakRDL-euvm

  Public
  Euvm plugin for SystemRDL's PeakRDL tool.

  Python

  •

  GNU General Public License v3.0

  •3•0•1•0•Updated Jul 24, 2023Jul 24, 2023

• test_constraints

  Public
  D

  •1•0•0•0•Updated Jun 14, 2023Jun 14, 2023

• riscv-bare-metal

  Public
  A RISC-V bare metal example

  C

  •

  MIT License

  •20•0•0•0•Updated May 26, 2022May 26, 2022