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    • tools

      Public
      Software Tools
      Makefile
      •
      Apache License 2.0
      •0•1•0•0•Updated Jan 2, 2025Jan 2, 2025

    • verilator-python

      Public
      Python/PyPI wrapper for Verilator
      hardwareverilogsystemverilogverilator
      Python
      •
      Apache License 2.0
      •0•0•0•0•Updated Jan 1, 2025Jan 1, 2025

    • uhdm-pypi

      Public
      PyPI Packaging for UHDM
      CMake
      •
      Apache License 2.0
      •0•0•0•0•Updated Dec 25, 2024Dec 25, 2024

    • litex-boards

      Public
      LiteX boards files
      Python
      •
      BSD 2-Clause "Simplified" License
      •294•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • litepcie

      Public
      Small footprint and configurable PCIe core
      Python
      •
      Other
      •120•1•0•0•Updated Dec 18, 2024Dec 18, 2024

    • litespi

      Public
      Small footprint and configurable SPI core
      Python
      •
      BSD 2-Clause "Simplified" License
      •23•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • synlig

      Public
      SystemVerilog support for Yosys
      Verilog
      •
      Apache License 2.0
      •23•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • basejump_stl

      Public
      BaseJump STL: A Standard Template Library for SystemVerilog
      SystemVerilog
      •
      Other
      •99•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • systemverilog-plugin

      Public
      SystemVerilog support for Yosys
      Verilog
      •
      Apache License 2.0
      •23•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • amaranth-boards

      Public
      Board definitions for Amaranth HDL
      Python
      •
      BSD 2-Clause "Simplified" License
      •110•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • dma_ip_drivers

      Public
      Xilinx QDMA IP Drivers
      C
      •426•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • brevitas

      Public
      Brevitas: neural network quantization in PyTorch
      Python
      •
      Other
      •199•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • nextpnr-xilinx

      Public
      Experimental flows using nextpnr for Xilinx devices
      C++
      •
      ISC License
      •44•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • openFPGALoader

      Public
      Universal utility for programming FPGA
      C++
      •
      Apache License 2.0
      •269•1•0•0•Updated Dec 18, 2024Dec 18, 2024

    • amaranth

      Public
      A modern hardware definition language and toolchain based on Python
      Python
      •
      BSD 2-Clause "Simplified" License
      •175•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • amaranth-soc

      Public
      System on Chip toolkit for Amaranth HDL
      Python
      •
      BSD 2-Clause "Simplified" License
      •32•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • cocotb

      Public
      cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •527•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • UHDM

      Public
      Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
      C++
      •
      Apache License 2.0
      •40•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •894•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • RapidWright

      Public
      Build Customized FPGA Implementations for Vivado
      Java
      •
      Other
      •111•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • prjxray

      Public
      Documenting the Xilinx 7-series bit-stream format.
      Python
      •
      ISC License
      •153•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      C++
      •
      GNU Lesser General Public License v3.0
      •627•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •148•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • verible

      Public
      Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
      C++
      •
      Other
      •217•1•0•0•Updated Dec 18, 2024Dec 18, 2024

    • hls4ml

      Public
      Machine learning on FPGAs using HLS
      C++
      •
      Apache License 2.0
      •423•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • liteeth

      Public
      Small footprint and configurable Ethernet core
      Python
      •
      Other
      •88•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • liteiclink

      Public
      Small footprint and configurable Inter-Chip communication cores
      Python
      •
      Other
      •27•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • Surelog

      Public
      SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
      C++
      •
      Apache License 2.0
      •68•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •40•0•0•0•Updated Dec 18, 2024Dec 18, 2024

    • litex

      Public
      Build your hardware, easily!
      C
      •
      Other
      •583•0•0•0•Updated Dec 18, 2024Dec 18, 2024