Load memory order violation in O3 CPU.

[cescuin]

Deal all,

As far as I know, the memory disambiguation approach of the O3 CPU executes loads that are predicted not to be dependent on older stores. Afterwards, when a store computes its address, it is compared with all the younger loads. If there is aliasing on the address there is a memory order violation.
There is a refetch-replay scheme implemented in the O3 core that makes the speculatively issued load and all subsequent instructions to be squashed and refetched again.

An alternative approach could be selective replay where both loads and load-dependent instructions are kept in the issue queue (for example) and they are "re-issued" upon the memory order violation.

I am wondering whether any alternative approach, such as a selective-replay one, is available in any branch or if anyone is willing to share any insight on this.

Thank you.