[bmv2] Incorrect behavior when assigning to bitvector slice

[vikramnathan]

[Using P4-16] Assigning to a bitvector slice produces an incorrect result when run on bmv2.

To reproduce:

register<bit<8>>(1) debug;
apply {
    bit<8> n = 8w0b11111111;
    n[7:4] = 4w0;
    debug.write(0, n);
}

Send a single packet through the switch. From the thrift CLI, run

>> register_read debug 0
debug[0] = 0

Expected: 15 ( = 0b00001111).

I'm attaching the source file for reference, which is a barebones switch containing the above snippet.
basic.p4.txt

Other comments:

• If n = 8w0 and is rewritten with n[7:4] = ~4w0, the above problem doesn't occur. debug[1] is as expected in both cases. Seems to only be a problem if the original bits are non-zero and the replaced bits are 0.
• This bug also occurs if the LSBs are reset.
• This works for other bit widths (I also tried 32 and 64 with the same result).
• Strangely, I observe the correct behavior if I write n to a register before resetting its MSBs:

register<bit<8>>(32w2) debug;
apply {
    bit<8> n = ~8w0;  // All 1s
    debug.write(0, n);
    n[7:4] = 4w0;
    debug.write(1, n);
}

>> register_read debug 0
debug[0] = 255
>> register_read debug 1
debug[1] = 15

which is expected.

• At p4c commit 6665263
• At behavioral-model commit f53451a280b7bb27b5f2b8410ab086122ee77526

[ChrisDodd]

Please close if you agree it is fixed

[vikramnathan]

Verified as fixed.