Running build.sh results in a complete flow from Verilog to binary bitstream.
- simple.v sets LED outputs to 1'b0, 1'b1 and clk. When uploaded to the FPGA it executes as expected.
- blinky.v Sets up a clock driven counter, blinks 8 LEDs
- blinky_int_osc.v Like above, but uses the internal oscillator instead of external one
- blinky_int_osc_pll.v Another blinky, but this one uses the built in pll
- rs232demo.v UART RX & TX controlling 5 LEDs
- bram_rom.v Uses a BRAM tile as ROM, blinks out the contents
- simple.py Creates the BELs, PIPs and wires for nextpnr. Utilizes files in the bitstream directory: chips.py, tiles.py, wires.py. The resulting routing looks sensible, e.g. build-blinky/log, starting at line 3357 and the IOTILEs appear to be configured correctly.
- write_fasm.py Mostly a copy of the same file from nextpnr: Does some mild transformation to PIP and BEL names to make them fasm compliant
- fasm_pack.py Reads in a fasm file generated by nextpnr-generic. Emits a textual bitstream that can be turned into a binary via agm-pack.py
- build-blinky/blinky-explain.txt The result of agm-unpack.py and agm-explain.py against the binary bitstream created in simple.sh. Used for sanity checks, and to compare against a similar file created from an
afgenerated bitstream: Blinky_explain.txt