@@ -1251,6 +1251,25 @@ pub unsafe fn _mm_loadr_ps(p: *const f32) -> __m128 {
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simd_shuffle4 ( a, a, [ 3 , 2 , 1 , 0 ] )
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}
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+ /// Loads unaligned 64-bits of integer data from memory into new vector.
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+ ///
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+ /// `mem_addr` does not need to be aligned on any particular boundary.
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+ ///
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+ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadu_si64)
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+ #[ inline]
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+ #[ target_feature( enable = "sse" ) ]
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+ #[ cfg_attr( test, assert_instr( movups) ) ]
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+ #[ stable( feature = "simd_x86" , since = "1.46.0" ) ]
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+ pub unsafe fn _mm_loadu_si64 ( mem_addr : * const u8 ) -> __m128i {
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+ let mut dst = _mm_setzero_si128 ( ) ;
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+ ptr:: copy_nonoverlapping (
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+ mem_addr,
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+ & mut dst as * mut __m128i as * mut u8 ,
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+ 8 , // == 64 bits == mem::size_of::<__m128i>() / 2
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+ ) ;
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+ dst
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+ }
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+
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/// Stores the upper half of `a` (64 bits) into memory.
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///
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/// This intrinsic corresponds to the `MOVHPS` instruction. The compiler may
@@ -3658,6 +3677,13 @@ mod tests {
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assert_eq_m128 ( r, e) ;
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}
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+ #[ simd_test( enable = "sse2" ) ]
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+ unsafe fn test_mm_loadu_si64 ( ) {
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+ let a = _mm_set_epi64x ( 5 , 0 ) ;
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+ let r = _mm_loadu_si64 ( & a as * const _ as * const _ ) ;
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+ assert_eq_m128i ( a, r) ;
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+ }
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+
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#[ simd_test( enable = "sse" ) ]
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unsafe fn test_mm_storeh_pi ( ) {
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let mut vals = [ 0.0f32 ; 8 ] ;
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