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Gate timing #18

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pcbsmoke opened this issue Nov 19, 2019 · 2 comments
Closed

Gate timing #18

pcbsmoke opened this issue Nov 19, 2019 · 2 comments

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@pcbsmoke
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These projects seam to have timing issues.? They need to be checked against the icetime utility. Even when using the nextpnr utility, which tries to improve timing by better placement, on a pc, the examples are below the 100Mhz.

@ombhilare999
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It seems icetime is obsolete now, I'm trying to check timing using --opt_timings flag in nextpnr.
I will post a detailed report here.

Regards,
omkar bhilare
ombhilare999@gmail.com

@ombhilare999
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I tested quite a few examples of beaglewire, which are documented here(https://beaglewire.github.io/Examples/)
All seems to have quite a good clock rate, One digital design engineer said about icetime features as following:

I'm not 100% sure for nextpnr but in general for fpga tools, once the constraint is met, it will stop trying to do anybetter (because why bother ... ).
And at those high frequency it's only a 900 ps path difference which can easily be explained by the router not bothering to find a better route for any of the random signal in there.

regards,
Omkar Bhilare
ombhilare999@gmail.com

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