sdram rd_busy should be rd_ready?

[osresearch]

Is the sense of the SDRAM's rd_busy incorrect? In the verilog code the logic is: https://github.com/pmezydlo/BeagleWire/blob/master/components/sdram_controller.v#L161

assign rd_ready = rd_ready_r;
[...]
   if (state == READ_READ)
      begin
      rd_data_r <= data_in_from_buffer;
      rd_ready_r <= 1'b1;
      end
    else
      rd_ready_r <= 1'b0;

Which makes rd_ready an active high signal when the read has data available. However, the sdram.c code calls it rd_busy and appears to spin waiting for it to go back to 0: https://github.com/pmezydlo/BeagleWire/blob/master/bridge_lib/sdram.c#L72 and

BeagleWire/bridge_lib/sdram.c

Line 102 in 31e636b

// waiting for clr rd ready bit

.

Although I just noticed that rd_ready_r is reset after one clk, so I'm updating my test to latch it to be sure that it is noticed by the host interface.

[ombhilare999]

Now we are using litedram + serv for sdram, it passed the litex mem test.
https://twitter.com/QwertyEmbedded/status/1418128122042486787

regards,
omkar bhilare
ombhilare999@gmail.com