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My goal would be to read it in order to perform equivalence checking on it for a project I am doing. I have considered tools such as s2v2 but it seems it is also not yet supported, however I was able to perform a simulation on it using iverilog.
I appreciate any suggestions or comments.
The text was updated successfully, but these errors were encountered:
Hi! I was willing to read the following system verilog:
However it seems it is a feature not yet implemented:
My goal would be to read it in order to perform equivalence checking on it for a project I am doing. I have considered tools such as s2v2 but it seems it is also not yet supported, however I was able to perform a simulation on it using iverilog.
I appreciate any suggestions or comments.
The text was updated successfully, but these errors were encountered: