Synching multiple RedPitaya boards

[michaelcroquette]

To overcome the limitations of having a finite number of inputs, outputs and IQ module and one card, we came up with a solution to synchronize two Red Pitaya boards on one external clock signal and then used a share trigger signal so the IQ modules are synced in phase over the two boards. This solution can be used to synchronize up to 4 boards in theory but we only tested it for two.

Clock signal generation

We need an external clock source, we use a VersaClock 6E Programmable Clock Generator (5P49V60) mounted on a SparkFun board. The board is programmable via I2C code using an Arduino library (Arduino code can be found here). It can generate four 125 MHz clock signals with LVDS level (the standard needed for the Red Pitayas clock signal). You then have to connect the Red Pitaya clock inputs to the board and you can synchronize up to 4 Red Pitayas (In our case we only needed to synchronize two).

Clock generator connections.

Red Pitaya Board modification

In order for the Red Pitaya board to use the external clock signal and not its own crystal clock signal, some soldering is needed. Unfortunately the official doc page is not responding anymore but a description of the procedure can be found here : https://forum.redpitaya.com/viewtopic.php?t=24704

IQ module synchronization

Warning : For now this feature is only implemented in the "modif_fpga_pfd" branch of pyrpl. On this branch, the pfd output option of the IQ module uses the CORDIC algorithm to give a precise estimation of the unwrap phase (more details here) . For FPGA resource reason, there is no IIR module but 4 PID modules on this branch.

The last step is to make sure that the demodulation modules all start with the same phase. Even if the clocks are synchronized, the relative phase between the IQ module depends on the timing at which they were started. So we add a connector between two digital Input/Output of the RedPitayas, and when one of the RedPitaya starts its IQ module it will send a signal to the other so that their internal reference always have the same phase relationship. This was implemented in the FPGA code in a simple way : the IQ will start when the DIO0_P (ext. trig) pin of the RP board is up. So by connecting the two pins of the two boards together and setting one as output and the other as input using the housekeeping module (hks).

output setup

input setup

Once the pins are connected, enabling expansion_P0 will start the IQs simultaneously over the two boards.

Alternatively you can use any external trigger signal to synchronize more than two RPs.
I hope this was clear and helpfuf, don't hesitate to ask more questions and give us feedback if you try to replicate this method !

[michaelcroquette]

I'm just adding a link to the original discussion #350 for those who would want to explore other way of synchronising RPs.