You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
The advantage of iverilog is that it is quick to make changes and re-run the simulation. I have pushed my version of the harness here https://github.com/peteasa/pyrpl_testbench/tree/main/fpga. This does not replace the vivado simulator, its just very quick to run with little overhead.
Also I like to keep the test code separate from the production code. It seems very easy to do that with the iverilog compiler.
I wonder if anyone has used iverilog to debug the FPGA? That plus gtkwave are a very powerful pair of applications to debug.
It would require a bit of setup with some test scripts but might help debug custom FPGA changes.
The text was updated successfully, but these errors were encountered: