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from dataclasses import dataclass , field
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- from typing import Generic , Literal , TypeVar , Union
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+ from typing import Literal , Union
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from qibolab ._core .components import OscillatorConfig
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"Controllers" ,
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]
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- V = TypeVar ("V" )
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-
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-
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- class PortDict (Generic [V ], dict [str , V ]):
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- """Dictionary that automatically converts keys to strings.
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-
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- Used to register input and output ports to controllers and Octaves
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- in the QUA config.
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- """
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-
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- def __setitem__ (self , key : Union [str , int ], value : V ):
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- super ().__setitem__ (str (key ), value )
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-
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@dataclass (frozen = True )
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class AnalogInput :
@@ -67,8 +54,12 @@ def update(self, config: MwFemOscillatorConfig):
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assert self .band == config .band
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assert self .sampling_rate == config .sampling_rate
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assert self .full_scale_power_dbm == config .power
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- assert config .upconverter not in self .upconverters
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- self .upconverters [config .upconverter ] = {"frequency" : config .frequency }
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+ if config .upconverter not in self .upconverters :
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+ self .upconverters [config .upconverter ] = {"frequency" : config .frequency }
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+ else :
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+ assert (
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+ config .frequency == self .upconverters [config .upconverter ]["frequency" ]
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+ )
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@dataclass (frozen = True )
@@ -116,10 +107,10 @@ class OctaveInput:
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class Controller :
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type : ModuleTypes = "opx1"
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"""https://docs.quantum-machines.co/latest/docs/Introduction/config/?h=opx10#controllers"""
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- analog_outputs : PortDict [ dict [str , dict ]] = field (default_factory = PortDict )
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- digital_outputs : PortDict [ dict [str , dict ]] = field (default_factory = PortDict )
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- analog_inputs : PortDict [ dict [str , Union [AnalogInput , MwFemInput ] ]] = field (
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- default_factory = PortDict
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+ analog_outputs : dict [int , dict ] = field (default_factory = dict )
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+ digital_outputs : dict [int , dict ] = field (default_factory = dict )
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+ analog_inputs : dict [int , Union [AnalogInput , MwFemInput ]] = field (
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+ default_factory = dict
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)
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def _set_default_inputs (self ):
@@ -150,14 +141,14 @@ def add_octave_input(self, port: int, config: QmAcquisitionConfig):
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@dataclass
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class Opx1000 :
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type : Literal ["opx1000" ] = "opx1000"
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- fems : dict [str , Controller ] = field (default_factory = PortDict )
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+ fems : dict [int , Controller ] = field (default_factory = dict )
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@dataclass
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class Octave :
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connectivity : Union [str , tuple [str , int ]]
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- RF_outputs : PortDict [ dict [str , OctaveOutput ]] = field (default_factory = PortDict )
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- RF_inputs : PortDict [ dict [str , OctaveInput ]] = field (default_factory = PortDict )
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+ RF_outputs : dict [int , OctaveOutput ] = field (default_factory = dict )
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+ RF_inputs : dict [int , OctaveInput ] = field (default_factory = dict )
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def __post_init__ (self ):
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if "/" in self .connectivity :
@@ -179,9 +170,10 @@ def process_controller_id(id: ControllerId):
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"""
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if isinstance (id , tuple ):
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con , fem = id
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- return con , str ( fem )
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+ return con , fem
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if "/" in id :
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- return id .split ("/" )
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+ con , fem = id .split ("/" )
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+ return con , int (fem )
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return id , None
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