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The diagonal compiler included as part of #498 makes its choice of where to insert CNOTs based solely on most frequently sighted ZZ Pauli pairs. This has the benefit of producing low-CNOT-count circuits, but there's no reason to think that they're low-depth or that they do a good job of respecting chip topology.
Investigate this insertion strategy. Can it be modified to be topology-sensitive? Can it be modified to improve circuit depth rather than total CNOT count?
The text was updated successfully, but these errors were encountered:
The diagonal compiler included as part of #498 makes its choice of where to insert
CNOT
s based solely on most frequently sightedZZ
Pauli pairs. This has the benefit of producing low-CNOT-count circuits, but there's no reason to think that they're low-depth or that they do a good job of respecting chip topology.Investigate this insertion strategy. Can it be modified to be topology-sensitive? Can it be modified to improve circuit depth rather than total CNOT count?
The text was updated successfully, but these errors were encountered: