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Revert "[portsorch] use ingress/egress disable for LAG member enable/disable (sonic-net#1166)"
This reverts commit 4edcc4d.
1 parent 53bd488 commit 9cc4810

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3 files changed

+23
-115
lines changed

3 files changed

+23
-115
lines changed

orchagent/portsorch.cpp

+16-78
Original file line numberDiff line numberDiff line change
@@ -2494,51 +2494,39 @@ void PortsOrch::doLagMemberTask(Consumer &consumer)
24942494
status = fvValue(i);
24952495
}
24962496

2497-
if (lag.m_members.find(port_alias) == lag.m_members.end())
2498-
{
2499-
/* Assert the port doesn't belong to any LAG already */
2500-
assert(!port.m_lag_id && !port.m_lag_member_id);
2501-
2502-
if (!addLagMember(lag, port))
2503-
{
2504-
it++;
2505-
continue;
2506-
}
2507-
}
2508-
25092497
/* Sync an enabled member */
25102498
if (status == "enabled")
25112499
{
2512-
/* enable collection first, distribution-only mode
2513-
* is not supported on Mellanox platform
2514-
*/
2515-
if (setCollectionOnLagMember(port, true) &&
2516-
setDistributionOnLagMember(port, true))
2500+
/* Duplicate entry */
2501+
if (lag.m_members.find(port_alias) != lag.m_members.end())
25172502
{
25182503
it = consumer.m_toSync.erase(it);
2504+
continue;
25192505
}
2506+
2507+
/* Assert the port doesn't belong to any LAG */
2508+
assert(!port.m_lag_id && !port.m_lag_member_id);
2509+
2510+
if (addLagMember(lag, port))
2511+
it = consumer.m_toSync.erase(it);
25202512
else
2521-
{
25222513
it++;
2523-
continue;
2524-
}
25252514
}
25262515
/* Sync an disabled member */
25272516
else /* status == "disabled" */
25282517
{
2529-
/* disable distribution first, distribution-only mode
2530-
* is not supported on Mellanox platform
2531-
*/
2532-
if (setDistributionOnLagMember(port, false) &&
2533-
setCollectionOnLagMember(port, false))
2518+
/* "status" is "disabled" at start when m_lag_id and
2519+
* m_lag_member_id are absent */
2520+
if (!port.m_lag_id || !port.m_lag_member_id)
25342521
{
25352522
it = consumer.m_toSync.erase(it);
2523+
continue;
25362524
}
2525+
2526+
if (removeLagMember(lag, port))
2527+
it = consumer.m_toSync.erase(it);
25372528
else
2538-
{
25392529
it++;
2540-
continue;
2541-
}
25422530
}
25432531
}
25442532
/* Remove a LAG member */
@@ -2556,13 +2544,9 @@ void PortsOrch::doLagMemberTask(Consumer &consumer)
25562544
}
25572545

25582546
if (removeLagMember(lag, port))
2559-
{
25602547
it = consumer.m_toSync.erase(it);
2561-
}
25622548
else
2563-
{
25642549
it++;
2565-
}
25662550
}
25672551
else
25682552
{
@@ -3356,52 +3340,6 @@ bool PortsOrch::removeLagMember(Port &lag, Port &port)
33563340
return true;
33573341
}
33583342

3359-
bool PortsOrch::setCollectionOnLagMember(Port &lagMember, bool enableCollection)
3360-
{
3361-
/* Port must be LAG member */
3362-
assert(port.m_lag_member_id);
3363-
3364-
sai_status_t status = SAI_STATUS_FAILURE;
3365-
sai_attribute_t attr {};
3366-
3367-
attr.id = SAI_LAG_MEMBER_ATTR_INGRESS_DISABLE;
3368-
attr.value.booldata = !enableCollection;
3369-
3370-
status = sai_lag_api->set_lag_member_attribute(lagMember.m_lag_member_id, &attr);
3371-
if (status != SAI_STATUS_SUCCESS)
3372-
{
3373-
SWSS_LOG_ERROR("Failed to %s collection on LAG member %s",
3374-
enableCollection ? "enable" : "disable",
3375-
lagMember.m_alias.c_str());
3376-
return false;
3377-
}
3378-
3379-
return true;
3380-
}
3381-
3382-
bool PortsOrch::setDistributionOnLagMember(Port &lagMember, bool enableDistribution)
3383-
{
3384-
/* Port must be LAG member */
3385-
assert(port.m_lag_member_id);
3386-
3387-
sai_status_t status = SAI_STATUS_FAILURE;
3388-
sai_attribute_t attr {};
3389-
3390-
attr.id = SAI_LAG_MEMBER_ATTR_EGRESS_DISABLE;
3391-
attr.value.booldata = !enableDistribution;
3392-
3393-
status = sai_lag_api->set_lag_member_attribute(lagMember.m_lag_member_id, &attr);
3394-
if (status != SAI_STATUS_SUCCESS)
3395-
{
3396-
SWSS_LOG_ERROR("Failed to %s distribution on LAG member %s",
3397-
enableDistribution ? "enable" : "disable",
3398-
lagMember.m_alias.c_str());
3399-
return false;
3400-
}
3401-
3402-
return true;
3403-
}
3404-
34053343
void PortsOrch::generateQueueMap()
34063344
{
34073345
if (m_isQueueMapGenerated)

orchagent/portsorch.h

-2
Original file line numberDiff line numberDiff line change
@@ -170,8 +170,6 @@ class PortsOrch : public Orch, public Subject
170170
bool removeLag(Port lag);
171171
bool addLagMember(Port &lag, Port &port);
172172
bool removeLagMember(Port &lag, Port &port);
173-
bool setCollectionOnLagMember(Port &lagMember, bool enableCollection);
174-
bool setDistributionOnLagMember(Port &lagMember, bool enableDistribution);
175173
void getLagMember(Port &lag, vector<Port> &portv);
176174

177175
bool addPort(const set<int> &lane_set, uint32_t speed, int an=0, string fec="");

tests/test_portchannel.py

+7-35
Original file line numberDiff line numberDiff line change
@@ -33,41 +33,13 @@ def test_Portchannel(self, dvs, testlog):
3333
assert len(lagms) == 1
3434

3535
(status, fvs) = lagmtbl.get(lagms[0])
36-
fvs = dict(fvs)
37-
assert status
38-
assert "SAI_LAG_MEMBER_ATTR_LAG_ID" in fvs
39-
assert fvs.pop("SAI_LAG_MEMBER_ATTR_LAG_ID") == lags[0]
40-
assert "SAI_LAG_MEMBER_ATTR_PORT_ID" in fvs
41-
assert dvs.asicdb.portoidmap[fvs.pop("SAI_LAG_MEMBER_ATTR_PORT_ID")] == "Ethernet0"
42-
assert "SAI_LAG_MEMBER_ATTR_INGRESS_DISABLE" in fvs
43-
assert fvs.pop("SAI_LAG_MEMBER_ATTR_INGRESS_DISABLE") == "false"
44-
assert "SAI_LAG_MEMBER_ATTR_EGRESS_DISABLE" in fvs
45-
assert fvs.pop("SAI_LAG_MEMBER_ATTR_EGRESS_DISABLE") == "false"
46-
assert not fvs
47-
48-
ps = swsscommon.ProducerStateTable(db, "LAG_MEMBER_TABLE")
49-
fvs = swsscommon.FieldValuePairs([("status", "disabled")])
50-
51-
ps.set("PortChannel0001:Ethernet0", fvs)
52-
53-
time.sleep(1)
54-
55-
lagmtbl = swsscommon.Table(asicdb, "ASIC_STATE:SAI_OBJECT_TYPE_LAG_MEMBER")
56-
lagms = lagmtbl.getKeys()
57-
assert len(lagms) == 1
58-
59-
(status, fvs) = lagmtbl.get(lagms[0])
60-
fvs = dict(fvs)
61-
assert status
62-
assert "SAI_LAG_MEMBER_ATTR_LAG_ID" in fvs
63-
assert fvs.pop("SAI_LAG_MEMBER_ATTR_LAG_ID") == lags[0]
64-
assert "SAI_LAG_MEMBER_ATTR_PORT_ID" in fvs
65-
assert dvs.asicdb.portoidmap[fvs.pop("SAI_LAG_MEMBER_ATTR_PORT_ID")] == "Ethernet0"
66-
assert "SAI_LAG_MEMBER_ATTR_INGRESS_DISABLE" in fvs
67-
assert fvs.pop("SAI_LAG_MEMBER_ATTR_INGRESS_DISABLE") == "true"
68-
assert "SAI_LAG_MEMBER_ATTR_EGRESS_DISABLE" in fvs
69-
assert fvs.pop("SAI_LAG_MEMBER_ATTR_EGRESS_DISABLE") == "true"
70-
assert not fvs
36+
for fv in fvs:
37+
if fv[0] == "SAI_LAG_MEMBER_ATTR_LAG_ID":
38+
assert fv[1] == lags[0]
39+
elif fv[0] == "SAI_LAG_MEMBER_ATTR_PORT_ID":
40+
assert dvs.asicdb.portoidmap[fv[1]] == "Ethernet0"
41+
else:
42+
assert False
7143

7244
# remove port channel member
7345
ps = swsscommon.ProducerStateTable(db, "LAG_MEMBER_TABLE")

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