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[RISCV][GISel] Remove some unneeded isel patterns.
These use riscv_ SDNodes that don't have GISel equivalents yet or for extensions that we haven't added tests for yet.
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‎llvm/lib/Target/RISCV/RISCVGISel.td‎

Lines changed: 0 additions & 179 deletions
Original file line numberDiff line numberDiff line change
@@ -244,79 +244,10 @@ def : PatGprGpr<srem, REMW, i32, i32>;
244244
def : PatGprGpr<urem, REMUW, i32, i32>;
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}
246246

247-
//===----------------------------------------------------------------------===//
248-
// Atomic RV64 i32 patterns not used by SelectionDAG
249-
//===----------------------------------------------------------------------===//
250-
251-
class PatGprGprA<SDPatternOperator OpNode, RVInst Inst, ValueType vt>
252-
: Pat<(vt (OpNode (XLenVT GPR:$rs1), (vt GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2)>;
253-
254-
multiclass AMOPat2<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
255-
list<Predicate> ExtraPreds = []> {
256-
let Predicates = !listconcat([HasStdExtA, NotHasStdExtZtso], ExtraPreds) in {
257-
def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_monotonic"),
258-
!cast<RVInst>(BaseInst), vt>;
259-
def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_acquire"),
260-
!cast<RVInst>(BaseInst#"_AQ"), vt>;
261-
def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_release"),
262-
!cast<RVInst>(BaseInst#"_RL"), vt>;
263-
def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_acq_rel"),
264-
!cast<RVInst>(BaseInst#"_AQ_RL"), vt>;
265-
def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_seq_cst"),
266-
!cast<RVInst>(BaseInst#"_AQ_RL"), vt>;
267-
}
268-
let Predicates = !listconcat([HasStdExtA, HasStdExtZtso], ExtraPreds) in {
269-
def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_monotonic"),
270-
!cast<RVInst>(BaseInst), vt>;
271-
def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_acquire"),
272-
!cast<RVInst>(BaseInst), vt>;
273-
def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_release"),
274-
!cast<RVInst>(BaseInst), vt>;
275-
def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_acq_rel"),
276-
!cast<RVInst>(BaseInst), vt>;
277-
def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_seq_cst"),
278-
!cast<RVInst>(BaseInst), vt>;
279-
}
280-
}
281-
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defm : AMOPat2<"atomic_swap_i32", "AMOSWAP_W", i32>;
283-
defm : AMOPat2<"atomic_load_add_i32", "AMOADD_W", i32>;
284-
defm : AMOPat2<"atomic_load_and_i32", "AMOAND_W", i32>;
285-
defm : AMOPat2<"atomic_load_or_i32", "AMOOR_W", i32>;
286-
defm : AMOPat2<"atomic_load_xor_i32", "AMOXOR_W", i32>;
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defm : AMOPat2<"atomic_load_max_i32", "AMOMAX_W", i32>;
288-
defm : AMOPat2<"atomic_load_min_i32", "AMOMIN_W", i32>;
289-
defm : AMOPat2<"atomic_load_umax_i32", "AMOMAXU_W", i32>;
290-
defm : AMOPat2<"atomic_load_umin_i32", "AMOMINU_W", i32>;
291-
292-
let Predicates = [HasStdExtA, IsRV64] in
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defm : PseudoCmpXchgPat<"atomic_cmp_swap_i32", PseudoCmpXchg32, i32>;
294-
295-
let Predicates = [HasAtomicLdSt] in {
296-
def : LdPat<atomic_load_8, LB, i32>;
297-
def : LdPat<atomic_load_16, LH, i32>;
298-
def : LdPat<atomic_load_32, LW, i32>;
299-
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def : StPat<atomic_store_8, SB, GPR, i32>;
301-
def : StPat<atomic_store_16, SH, GPR, i32>;
302-
def : StPat<atomic_store_32, SW, GPR, i32>;
303-
}
304-
305-
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//===----------------------------------------------------------------------===//
307248
// Zb* RV64 i32 patterns not used by SelectionDAG.
308249
//===----------------------------------------------------------------------===//
309250

310-
def zexti16i32 : ComplexPattern<i32, 1, "selectZExtBits<16>">;
311-
def zexti8i32 : ComplexPattern<i32, 1, "selectZExtBits<8>">;
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def BCLRMaski32 : ImmLeaf<i32, [{
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return !isInt<12>(Imm) && isPowerOf2_32(~Imm);
315-
}]>;
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def SingleBitSetMaski32 : ImmLeaf<i32, [{
317-
return !isInt<12>(Imm) && isPowerOf2_32(Imm);
318-
}]>;
319-
320251
let Predicates = [HasStdExtZbb, IsRV64] in {
321252
def : PatGpr<ctlz, CLZW, i32>;
322253
def : PatGpr<cttz, CTZW, i32>;
@@ -328,10 +259,6 @@ def : Pat<(i32 (sext_inreg GPR:$rs1, i16)), (SEXT_H GPR:$rs1)>;
328259
def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV64 GPR:$rs)>;
329260
} // Predicates = [HasStdExtZbb, IsRV64]
330261

331-
let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV64] in {
332-
def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (PACKW GPR:$rs, (XLenVT X0))>;
333-
}
334-
335262
let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
336263
def : Pat<(i32 (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
337264
def : Pat<(i32 (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>;
@@ -346,21 +273,6 @@ def : Pat<(i32 (rotl GPR:$rs1, uimm5i32:$rs2)),
346273
(RORIW GPR:$rs1, (ImmSubFrom32 uimm5i32:$rs2))>;
347274
} // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
348275

349-
let Predicates = [HasStdExtZbkb, IsRV64] in {
350-
def : Pat<(or (and (shl GPR:$rs2, (i64 8)), 0xFFFF),
351-
(zexti8i32 (i32 GPR:$rs1))),
352-
(PACKH GPR:$rs1, GPR:$rs2)>;
353-
def : Pat<(or (shl (zexti8i32 (i32 GPR:$rs2)), (i64 8)),
354-
(zexti8i32 (i32 GPR:$rs1))),
355-
(PACKH GPR:$rs1, GPR:$rs2)>;
356-
def : Pat<(and (anyext (or (shl GPR:$rs2, (XLenVT 8)),
357-
(zexti8i32 (i32 GPR:$rs1)))), 0xFFFF),
358-
(PACKH GPR:$rs1, GPR:$rs2)>;
359-
360-
def : Pat<(i32 (or (shl GPR:$rs2, (i64 16)), (zexti16i32 (i32 GPR:$rs1)))),
361-
(PACKW GPR:$rs1, GPR:$rs2)>;
362-
} // Predicates = [HasStdExtZbkb, IsRV64]
363-
364276
let Predicates = [HasStdExtZba, IsRV64] in {
365277
def : Pat<(shl (i64 (zext i32:$rs1)), uimm5:$shamt),
366278
(SLLI_UW GPR:$rs1, uimm5:$shamt)>;
@@ -373,96 +285,5 @@ foreach i = {1,2,3} in {
373285
defvar shxadd = !cast<Instruction>("SH"#i#"ADD");
374286
def : Pat<(i32 (add_like_non_imm12 (shl GPR:$rs1, (i32 i)), GPR:$rs2)),
375287
(shxadd GPR:$rs1, GPR:$rs2)>;
376-
def : Pat<(i32 (riscv_shl_add GPR:$rs1, (i32 i), GPR:$rs2)),
377-
(shxadd GPR:$rs1, GPR:$rs2)>;
378-
}
379-
}
380-
381-
let Predicates = [HasStdExtZbs, IsRV64] in {
382-
def : Pat<(i32 (and (not (shiftop<shl> 1, (i64 GPR:$rs2))), GPR:$rs1)),
383-
(BCLR GPR:$rs1, GPR:$rs2)>;
384-
def : Pat<(i32 (and (rotl -2, (i64 GPR:$rs2)), GPR:$rs1)),
385-
(BCLR GPR:$rs1, GPR:$rs2)>;
386-
def : Pat<(i32 (or (shiftop<shl> 1, (i64 GPR:$rs2)), GPR:$rs1)),
387-
(BSET GPR:$rs1, GPR:$rs2)>;
388-
def : Pat<(i32 (xor (shiftop<shl> 1, (i64 GPR:$rs2)), GPR:$rs1)),
389-
(BINV GPR:$rs1, GPR:$rs2)>;
390-
def : Pat<(i32 (and (shiftop<srl> GPR:$rs1, (i64 GPR:$rs2)), 1)),
391-
(BEXT GPR:$rs1, GPR:$rs2)>;
392-
def : Pat<(i64 (and (anyext (i32 (shiftop<srl> GPR:$rs1, (i64 GPR:$rs2)))), 1)),
393-
(BEXT GPR:$rs1, GPR:$rs2)>;
394-
395-
def : Pat<(i32 (shiftop<shl> 1, (i64 GPR:$rs2))),
396-
(BSET (XLenVT X0), GPR:$rs2)>;
397-
def : Pat<(i32 (not (shiftop<shl> -1, (i64 GPR:$rs2)))),
398-
(ADDI (i32 (BSET (XLenVT X0), GPR:$rs2)), -1)>;
399-
400-
def : Pat<(i32 (and (srl GPR:$rs1, uimm5:$shamt), (i32 1))),
401-
(BEXTI GPR:$rs1, uimm5:$shamt)>;
402-
403-
def : Pat<(i32 (and GPR:$rs1, BCLRMaski32:$mask)),
404-
(BCLRI GPR:$rs1, (i64 (BCLRXForm $mask)))>;
405-
def : Pat<(i32 (or GPR:$rs1, SingleBitSetMaski32:$mask)),
406-
(BSETI GPR:$rs1, (i64 (SingleBitSetMaskToIndex $mask)))>;
407-
def : Pat<(i32 (xor GPR:$rs1, SingleBitSetMaski32:$mask)),
408-
(BINVI GPR:$rs1, (i64 (SingleBitSetMaskToIndex $mask)))>;
409-
} // Predicates = [HasStdExtZbs, IsRV64]
410-
411-
//===----------------------------------------------------------------------===//
412-
// XTHead RV64 i32 patterns not used by SelectionDAG.
413-
//===----------------------------------------------------------------------===//
414-
415-
def sexti16i32 : ComplexPattern<i32, 1, "selectSExtBits<16>">;
416-
417-
let Predicates = [HasVendorXTHeadMemIdx, IsRV64] in {
418-
defm : StoreUpdatePat<post_truncsti8, TH_SBIA, i32>;
419-
defm : StoreUpdatePat<pre_truncsti8, TH_SBIB, i32>;
420-
defm : StoreUpdatePat<post_truncsti16, TH_SHIA, i32>;
421-
defm : StoreUpdatePat<pre_truncsti16, TH_SHIB, i32>;
422-
423-
defm : StIdxPat<truncstorei8, TH_SRB, GPR, i32>;
424-
defm : StIdxPat<truncstorei16, TH_SRH, GPR, i32>;
425-
426-
defm : StZextIdxPat<truncstorei8, TH_SURB, GPR, i32>;
427-
defm : StZextIdxPat<truncstorei16, TH_SURH, GPR, i32>;
428-
defm : StZextIdxPat<store, TH_SURW, GPR, i32>;
429288
}
430-
431-
let Predicates = [HasVendorXTHeadCondMov, IsRV64] in {
432-
def : Pat<(select (XLenVT GPR:$cond), (i32 GPR:$a), (i32 GPR:$b)),
433-
(TH_MVEQZ GPR:$a, GPR:$b, GPR:$cond)>;
434-
def : Pat<(select (XLenVT GPR:$cond), (i32 GPR:$a), (i32 0)),
435-
(TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;
436-
def : Pat<(select (XLenVT GPR:$cond), (i32 0), (i32 GPR:$b)),
437-
(TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
438-
439-
def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (i32 GPR:$a), (i32 GPR:$b)),
440-
(TH_MVNEZ GPR:$a, GPR:$b, GPR:$cond)>;
441-
def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (i32 GPR:$a), (i32 GPR:$b)),
442-
(TH_MVEQZ GPR:$a, GPR:$b, GPR:$cond)>;
443-
def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (i32 GPR:$a), (i32 0)),
444-
(TH_MVNEZ GPR:$a, (XLenVT X0), GPR:$cond)>;
445-
def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (i32 GPR:$a), (i32 0)),
446-
(TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;
447-
def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (i32 0), (i32 GPR:$b)),
448-
(TH_MVEQZ GPR:$b, (XLenVT X0), GPR:$cond)>;
449-
def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (i32 0), (i32 GPR:$b)),
450-
(TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
451-
} // Predicates = [HasVendorXTHeadCondMov]
452-
453-
let Predicates = [HasVendorXTHeadMac, IsRV64] in {
454-
// mulaw, mulsw are available only in RV64.
455-
def : Pat<(i32 (add GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
456-
(TH_MULAW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
457-
def : Pat<(i32 (sub GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
458-
(TH_MULSW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
459-
// mulah, mulsh produce a sign-extended result.
460-
def : Pat<(i32 (add GPR:$rd,
461-
(mul (sexti16i32 (i32 GPR:$rs1)),
462-
(sexti16i32 (i32 GPR:$rs2))))),
463-
(TH_MULAH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
464-
def : Pat<(i32 (sub GPR:$rd,
465-
(mul (sexti16i32 (i32 GPR:$rs1)),
466-
(sexti16i32 (i32 GPR:$rs2))))),
467-
(TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
468289
}

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