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[Experimental] Create a BURS-style instruction selector
Experiment to create a BURS-style instruction selector for LLVM. For the algorithm to construct the tables and how to use them, see [Proebsting 1995, BURS Automata Generation](https://dl.acm.org/doi/pdf/10.1145/203095.203098) For the extension of tree parsing to DAGs, see [Ertl 1999; Optimal Code Selection in DAGs](https://dl.acm.org/doi/pdf/10.1145/292540.292562) For the integration of constraints, see [Thier, Ertl, Krall 2018; Fast and Flexible Instruction Selection with Constraints](https://publik.tuwien.ac.at/files/publik_277344.pdf) For the hard-coded output values, see [Fraser, Henry 1991; Hard-coding Bottom-up Code Generation Tables to Save Time and Space](http://tfeng.me/papers/fh91hard.pdf)
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‎llvm/include/llvm/CodeGen/GlobalISel/BURSInstructionSelect.h

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//== llvm/CodeGen/GlobalISel/BURSInstructionSelect.h -------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file This file describes the interface of the MachineFunctionPass
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/// responsible for selecting (possibly generic) machine instructions to
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/// target-specific instructions.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_BURSINSTRUCTIONSELECT_H
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#define LLVM_CODEGEN_GLOBALISEL_BURSINSTRUCTIONSELECT_H
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Support/CodeGen.h"
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namespace llvm {
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class BlockFrequencyInfo;
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class ProfileSummaryInfo;
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/// This pass is responsible for selecting generic machine instructions to
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/// target-specific instructions. It relies on the InstructionSelector provided
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/// by the target.
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/// Selection is done by examining blocks in post-order, and instructions are
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/// first labelled in normal order, and then reduced in reverse order.
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///
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/// \post for all inst in MF: not isPreISelGenericOpcode(inst.opcode)
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class BURSInstructionSelect : public MachineFunctionPass {
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public:
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static char ID;
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StringRef getPassName() const override { return "BURSInstructionSelect"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties()
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.set(MachineFunctionProperties::Property::IsSSA)
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.set(MachineFunctionProperties::Property::Legalized)
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.set(MachineFunctionProperties::Property::RegBankSelected);
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}
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MachineFunctionProperties getSetProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::Selected);
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}
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BURSInstructionSelect(CodeGenOptLevel OL);
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BURSInstructionSelect();
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bool runOnMachineFunction(MachineFunction &MF) override;
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protected:
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BlockFrequencyInfo *BFI = nullptr;
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ProfileSummaryInfo *PSI = nullptr;
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CodeGenOptLevel OptLevel = CodeGenOptLevel::None;
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};
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} // End namespace llvm.
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#endif

‎llvm/include/llvm/CodeGen/GlobalISel/BURSInstructionSelector.h

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//===- llvm/CodeGen/GlobalISel/BURSInstructionSelector.h --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file declares the API for the BURS instruction selector.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_BURSINSTRUCTIONSELECTOR_H
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#define LLVM_CODEGEN_GLOBALISEL_BURSINSTRUCTIONSELECTOR_H
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#include <llvm/ADT/DenseMap.h>
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#include <cstdint>
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namespace llvm {
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class BlockFrequencyInfo;
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class CodeGenCoverage;
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class GISelKnownBits;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class MachineOptimizationRemarkEmitter;
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class ProfileSummaryInfo;
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class TargetPassConfig;
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class BURSInstructionSelector {
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// The mapping of MIs to a state.
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DenseMap<MachineInstr *, uint32_t> States;
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public:
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virtual ~BURSInstructionSelector();
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// The tablegen-erated functions.
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virtual void label(MachineInstr &I) = 0;
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virtual bool reduce(MachineInstr &I) = 0;
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protected:
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/// A lowering phase that runs before any selection attempts.
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/// Returns true if the instruction was modified.
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virtual bool preISelLower(MachineInstr &I) { return false; }
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/// An early selection function that runs before the reduce() call.
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/// Returns true if the instruction was selected.
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virtual bool earlySelect(MachineInstr &I) { return false; }
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/// Select the (possibly generic) instruction \p I to only use target-specific
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/// opcodes. It is OK to insert multiple instructions, but they cannot be
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/// generic pre-isel instructions.
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///
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/// \returns whether selection succeeded.
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/// \pre I.getParent() && I.getParent()->getParent()
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/// \post
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/// if returns true:
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/// for I in all mutated/inserted instructions:
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/// !isPreISelGenericOpcode(I.getOpcode())
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virtual bool select(MachineInstr &I) = 0;
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public:
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void setTargetPassConfig(const TargetPassConfig *T) { TPC = T; }
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void setRemarkEmitter(MachineOptimizationRemarkEmitter *M) { MORE = M; }
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protected:
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CodeGenCoverage *CoverageInfo = nullptr;
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GISelKnownBits *KB = nullptr;
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MachineFunction *MF = nullptr;
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ProfileSummaryInfo *PSI = nullptr;
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BlockFrequencyInfo *BFI = nullptr;
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// For some predicates, we need to track the current MBB.
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MachineBasicBlock *CurMBB = nullptr;
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public:
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virtual void setupGeneratedPerFunctionState(MachineFunction &MF) = 0;
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/// Setup per-MF executor state.
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virtual void setupMF(MachineFunction &MF, GISelKnownBits *KB,
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CodeGenCoverage *CoverageInfo = nullptr,
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ProfileSummaryInfo *PSI = nullptr,
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BlockFrequencyInfo *BFI = nullptr) {
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this->CoverageInfo = CoverageInfo;
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this->KB = KB;
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this->MF = &MF;
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this->PSI = PSI;
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this->BFI = BFI;
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this->CurMBB = nullptr;
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setupGeneratedPerFunctionState(MF);
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}
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void setCurMBB(MachineBasicBlock *CurMBB) {
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this->CurMBB = CurMBB;
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// Clear the recorded states for a new MBB.
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// Cannot give a good default, since MBB.size() is in O(N).
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States.clear();
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}
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protected:
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const TargetPassConfig *TPC = nullptr;
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MachineOptimizationRemarkEmitter *MORE = nullptr;
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};
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} // namespace llvm
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#endif

‎llvm/include/llvm/CodeGen/TargetSubtargetInfo.h

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namespace llvm {
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class APInt;
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class BURSInstructionSelector;
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class MachineFunction;
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class ScheduleDAGMutation;
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class CallLowering;
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return nullptr;
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}
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virtual BURSInstructionSelector *getBURSInstructionSelector() const {
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return nullptr;
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}
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/// Target can subclass this hook to select a different DAG scheduler.
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virtual RegisterScheduler::FunctionPassCtor
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getDAGScheduler(CodeGenOptLevel) const {

‎llvm/include/llvm/InitializePasses.h

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void initializeInferAddressSpacesPass(PassRegistry &);
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void initializeInstSimplifyLegacyPassPass(PassRegistry &);
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void initializeInstructionCombiningPassPass(PassRegistry &);
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void initializeBURSInstructionSelectPass(PassRegistry&);
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void initializeInstructionSelectPass(PassRegistry &);
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void initializeInterleavedAccessPass(PassRegistry &);
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void initializeInterleavedLoadCombinePass(PassRegistry &);

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