|
13 | 13 | #error "This file is intended for NVPTX targets or offloading to NVPTX"
|
14 | 14 | #endif
|
15 | 15 |
|
16 |
| -#ifndef __CUDA_ARCH__ |
17 |
| -#define __CUDA_ARCH__ 0 |
| 16 | +#ifndef __GPUINTRIN_H |
| 17 | +#error "Never use <nvptxintrin.h> directly; include <gpuintrin.h> instead" |
18 | 18 | #endif
|
19 | 19 |
|
20 |
| -#include <stdint.h> |
21 |
| - |
22 |
| -#if !defined(__cplusplus) |
23 |
| -_Pragma("push_macro(\"bool\")"); |
24 |
| -#define bool _Bool |
| 20 | +#ifndef __CUDA_ARCH__ |
| 21 | +#define __CUDA_ARCH__ 0 |
25 | 22 | #endif
|
26 | 23 |
|
27 | 24 | _Pragma("omp begin declare target device_type(nohost)");
|
@@ -153,18 +150,6 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t __idx, uint32_t __x,
|
153 | 150 | ((__gpu_num_lanes() - __width) << 8u) | 0x1f);
|
154 | 151 | }
|
155 | 152 |
|
156 |
| -// Shuffles the the lanes inside the warp according to the given index. |
157 |
| -_DEFAULT_FN_ATTRS static __inline__ uint64_t |
158 |
| -__gpu_shuffle_idx_u64(uint64_t __lane_mask, uint32_t __idx, uint64_t __x, |
159 |
| - uint32_t __width) { |
160 |
| - uint32_t __hi = (uint32_t)(__x >> 32ull); |
161 |
| - uint32_t __lo = (uint32_t)(__x & 0xFFFFFFFF); |
162 |
| - uint32_t __mask = (uint32_t)__lane_mask; |
163 |
| - return ((uint64_t)__gpu_shuffle_idx_u32(__mask, __idx, __hi, __width) |
164 |
| - << 32ull) | |
165 |
| - ((uint64_t)__gpu_shuffle_idx_u32(__mask, __idx, __lo, __width)); |
166 |
| -} |
167 |
| - |
168 | 153 | // Returns a bitmask marking all lanes that have the same value of __x.
|
169 | 154 | _DEFAULT_FN_ATTRS static __inline__ uint64_t
|
170 | 155 | __gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
|
@@ -263,8 +248,4 @@ _DEFAULT_FN_ATTRS static __inline__ void __gpu_thread_suspend(void) {
|
263 | 248 | _Pragma("omp end declare variant");
|
264 | 249 | _Pragma("omp end declare target");
|
265 | 250 |
|
266 |
| -#if !defined(__cplusplus) |
267 |
| -_Pragma("pop_macro(\"bool\")"); |
268 |
| -#endif |
269 |
| - |
270 | 251 | #endif // __NVPTXINTRIN_H
|
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