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Considering ATS=1, PRIV=1 (ATS privileged request), a read for execute request with the following settings:
PV=1, DC.PDTV=1, PC.ENS=1, PC.SUM=1
VS PTE U=1, XWR=3'b111
Reference model responds to this request as success with
perm_X=0, perm_W=0, perm_R=0.
Is that correct? Shouldn't it be the following:
perm_X=0, perm_W=1, perm_R=1
The related code is as follows:
// * Write/AMO guest-page fault (cause = 23)
// * PDT entry not valid (cause = 266)
// * MSI PTE not valid (cause = 262)
if ( (cause == 12) || (cause == 13) || (cause == 15) || (cause == 20) || (cause == 21) ||
(cause == 23) || (cause == 266) || (cause == 262) ) {
// Return response with R=W=0. The rest of the field are undefined. The reference
// model sets them to 0.
vs_pte.raw = g_pte.raw = 0;
is_msi = 0;
page_sz = PAGESIZE;
goto step_20;
Where vs_pte.raw = g_pte.raw = 0 causes this conflict. The reference model always returns a success response against such a page fault occurring to an ATS request, what bothers us a lot is the granted permission fields.
The ambiguity we can see from the specification:
If the translation request has a PASID with "Privilege Mode Requested“ field set to 1, then the request targets privileged memory. If the U-bit that indicates if the page is accessible to user mode is 1 and the SUM bit in the ta field of the process-context is 0 then a Success response with R and W bits set to 0 is generated.
If the translation could be successfully completed but the requested permission are not present (Execute requested but no execute permission; no-write not requested and no write permission; no read permission) then a Success response is returned with the denied permission (R, W or X) set to 0 and the other permission bits set to the value determined from the page table. The X permission is granted only if the R permission is also granted. Execute-only translations are not compatible with PCIe ATS as PCIe requires read permission to be granted if the execute permission is granted.
The text was updated successfully, but these errors were encountered:
The SUM bit only applies to read and write; it is not applicable to requests for execution. For a request to execute, the PTE with U=1 is not valid since that PTE is only for Unprivileged accesses. Hence it is treated as not being able to complete the translation.
Considering ATS=1, PRIV=1 (ATS privileged request), a read for execute request with the following settings:
Reference model responds to this request as success with
perm_X=0, perm_W=0, perm_R=0.
Is that correct? Shouldn't it be the following:
perm_X=0, perm_W=1, perm_R=1
The related code is as follows:
Where vs_pte.raw = g_pte.raw = 0 causes this conflict. The reference model always returns a success response against such a page fault occurring to an ATS request, what bothers us a lot is the granted permission fields.
The ambiguity we can see from the specification:
If the translation request has a PASID with "Privilege Mode Requested“ field set to 1, then the request targets privileged memory. If the U-bit that indicates if the page is accessible to user mode is 1 and the SUM bit in the ta field of the process-context is 0 then a Success response with R and W bits set to 0 is generated.
If the translation could be successfully completed but the requested permission are not present (Execute requested but no execute permission; no-write not requested and no write permission; no read permission) then a Success response is returned with the denied permission (R, W or X) set to 0 and the other permission bits set to the value determined from the page table. The X permission is granted only if the R permission is also granted. Execute-only translations are not compatible with PCIe ATS as PCIe requires read permission to be granted if the execute permission is granted.
The text was updated successfully, but these errors were encountered: