overview.adoc

Bit-manipulation a, b, c and s extensions grouped for public review and ratification

The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction. While the instructions are intended to have general use, some instructions are more useful in some domains than others. Hence, several smaller bitmanip extensions are provided, rather than one large extension. Each of these smaller extensions is grouped by common function and use case, and each has its own Zb*-extension name.

Each bitmanip extension includes a group of several bitmanip instructions that have similar purposes and that can often share the same logic. Some instructions are available in only one extension while others are available in several. The instructions have mnemonics and encodings that are independent of the extensions in which they appear. Thus, when implementing extensions with overlapping instructions, there is no redundancy in logic or encoding.

The bitmanip extensions are defined for RV32 and RV64. Most of the instructions are expected to be forward compatible with RV128. While the shift-immediate instructions are defined to have at most a 6-bit immediate field, a 7th bit is available in the encoding space should this be needed for RV128.

Word Instructions

The bitmanip extension follows the convention in RV64 that w-suffixed instructions (without a dot before the w) ignore the upper 32 bits of their inputs, operate on the least-significant 32-bits as signed values and produce a 32-bit signed result that is sign-extended to XLEN.

Bitmanip instructions with the suffix .uw have one operand that is an unsigned 32-bit value that is extracted from the least significant 32 bits of the specified register. Other than that, these perform full XLEN operations.

Bitmanip instructions with the suffix .b, .h and .w only look at the least significant 8-bits, 16-bits and 32-bits of the input (respectively) and produce an XLEN-wide result that is sign-extended or zero-extended, based on the specific instruction.

Pseudocode for instruction semantics

The semantics of each instruction in [insns] is expressed in a SAIL-like syntax.

Extensions

The first group of bitmanip extensions to be released for Public Review are:

• [zba]

• [zbb]

• [zbc]

• [zbs]

Below is a list of all of the instructions (and pseudoinstructions) that are included in these extensions along with their specific mapping:

RV32	RV64	Mnemonic	Instruction	Zba	Zbb	Zbc	Zbs
	✓	add.uw rd, rs1, rs2	[insns-add_uw]	✓
✓	✓	andn rd, rs1, rs2	[insns-andn]		✓
✓	✓	clmul rd, rs1, rs2	[insns-clmul]			✓
✓	✓	clmulh rd, rs1, rs2	[insns-clmulh]			✓
✓	✓	clmulr rd, rs1, rs2	[insns-clmulr]			✓
✓	✓	clz rd, rs	[insns-clz]		✓
	✓	clzw rd, rs	[insns-clzw]		✓
✓	✓	cpop rd, rs	[insns-cpop]		✓
	✓	cpopw rd, rs	[insns-cpopw]		✓
✓	✓	ctz rd, rs	[insns-ctz]		✓
	✓	ctzw rd, rs	[insns-ctzw]		✓
✓	✓	max rd, rs1, rs2	[insns-max]		✓
✓	✓	maxu rd, rs1, rs2	[insns-maxu]		✓
✓	✓	min rd, rs1, rs2	[insns-min]		✓
✓	✓	minu rd, rs1, rs2	[insns-minu]		✓
✓	✓	orc.b rd, rs1, rs2	[insns-orc_b]		✓
✓	✓	orn rd, rs1, rs2	[insns-orn]		✓
✓	✓	rev8 rd, rs	[insns-rev8]		✓
✓	✓	rol rd, rs1, rs2	[insns-rol]		✓
	✓	rolw rd, rs1, rs2	[insns-rolw]		✓
✓	✓	ror rd, rs1, rs2	[insns-ror]		✓
✓	✓	rori rd, rs1, shamt	[insns-rori]		✓
	✓	roriw rd, rs1, shamt	[insns-roriw]		✓
	✓	rorw rd, rs1, rs2	[insns-rorw]		✓
✓	✓	bclr rd, rs1, rs2	[insns-bclr]				✓
✓	✓	bclri rd, rs1, imm	[insns-bclri]				✓
✓	✓	bext rd, rs1, rs2	[insns-bext]				✓
✓	✓	bexti rd, rs1, imm	[insns-bexti]				✓
✓	✓	binv rd, rs1, rs2	[insns-binv]				✓
✓	✓	binvi rd, rs1, imm	[insns-binvi]				✓
✓	✓	bset rd, rs1, rs2	[insns-bset]				✓
✓	✓	bseti rd, rs1, imm	[insns-bseti]				✓
✓	✓	sext.b rd, rs	[insns-sext_b]		✓
✓	✓	sext.h rd, rs	[insns-sext_h]		✓
✓	✓	sh1add rd, rs1, rs2	[insns-sh1add]	✓
	✓	sh1add.uw rd, rs1, rs2	[insns-sh1add_uw]	✓
✓	✓	sh2add rd, rs1, rs2	[insns-sh2add]	✓
	✓	sh2add.uw rd, rs1, rs2	[insns-sh2add_uw]	✓
✓	✓	sh3add rd, rs1, rs2	[insns-sh3add]	✓
	✓	sh3add.uw rd, rs1, rs2	[insns-sh3add_uw]	✓
	✓	slli.uw rd, rs1, imm	[insns-slli_uw]	✓
✓	✓	xnor rd, rs1, rs2	[insns-xnor]		✓
✓	✓	zext.h rd, rs	[insns-zext_h]		✓
	✓	zext.w rd, rs	[insns-add_uw]	✓