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Could we support Zvbc
(Carryless Multiplication) for SEW32?
#309
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I think you don't need the widening if you work 64-bit wide chunks and uses R is a 32-bit value (static, only depends on the CRC) that is zero extended to a 64-bit element once and for all. You need to compute a 128-bit accumulator:
Eventually (at the end), the accumulator and the final 128-bit of the message needs to be properly padded and reduced |
Here, the most useful instruction would be a A smaller SEW may be less wasteful powerwise (the |
This was discussed during April 6th task group and it appears that this proposal could be quite useful in particular to allow 32-bit implementation ( (This is not an official message from the TG, just my transcript of my understanding of the meeting discussions) |
The final decision has been to leave the SEW=32 variant out of the current vector crypto specification. Should there be a need for this instruction for Zve32* implementations, we are leaving the option open to add them in a subsequent extension, perhaps as a FastTrack. |
If we could use zvbc with SEW32, we could get better performance for CRC32 algorithm.
We could still use the current SEW32 instructions, but we need the additional widening from SEW32 to 64 and masking the unused MSB parts.
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