Merge #69

69: compile on stable r=japaric a=japaric

with these changes this crate compiles on stable

Co-authored-by: Jorge Aparicio <jorge@japaric.io>

Author: bors[bot]

Diff for: .travis.yml

@@ -0,0 +1,85 @@
+language: rust
+
+matrix:
+  include:
+    - env: TARGET=x86_64-unknown-linux-gnu
+
+    - env: TARGET=thumbv6m-none-eabi
+      rust: beta
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
+    - env: TARGET=thumbv7m-none-eabi
+      rust: beta
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
+    - env: TARGET=thumbv7em-none-eabi
+      rust: beta
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
+    - env: TARGET=thumbv7em-none-eabihf
+      rust: beta
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
+    - env: TARGET=thumbv6m-none-eabi
+      rust: nightly
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
+    - env: TARGET=thumbv7m-none-eabi
+      rust: nightly
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
+    - env: TARGET=thumbv7em-none-eabi
+      rust: nightly
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
+    - env: TARGET=thumbv7em-none-eabihf
+      rust: nightly
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
+before_install: set -e
+
+install:
+  - bash ci/install.sh
+
+script:
+  - bash ci/script.sh
+
+after_script: set +e
+
+cache: cache
+
+before_cache:
+  - chmod -R a+r $HOME/.cargo;
+
+branches:
+  only:
+    - staging
+    - trying
+
+notifications:
+  email:
+    on_success: never

Diff for: CHANGELOG.md

@@ -7,6 +7,43 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.5.0] - 2018-05-12
+
+### Added
+
+- An `entry!` macro to set the entry point of the program.
+
+- A `heap_start` function that returns a pointer into the start of the heap region.
+
+- A `device` feature. When disabled this crate provides the interrupt vectors; when enabled the
+  interrupt vectors are expected to be provided by another crate. Read the documentation for
+  details.
+
+### Changed
+
+- This crate now compiles on the beta and stable channels.
+
+- [breaking-change] this crate now requires `arm-none-eabi-gcc` to be installed and available in
+  `$PATH` to compile.
+
+- [breaking-change] the `start` lang item has been removed. The standard `main` interface won't
+  work. Instead use `#![no_main]` and the `entry!` macro. See documentation for details.
+
+- [breaking-change] the `default_handler!` macro has been merged into the `exception!` macro. Use
+  `exception!(*, ..)` to set the default exception handler.
+
+- [breaking-change] there's no weak default handler so a default handler must be defined by the
+  application, or one of its dependencies.
+
+- [breaking-change] the syntax of the third argument of the `exception!` handler has changed. See
+  the documentation of the macro for details.
+
+- [breaking-change] the exception names that the `exception!` macro accepts has changed to match the
+  CMSIS specification. See the documentation of the macro for the list of names it accepts.
+
+- [breaking-change] The number of symbol interfaces has been reduced. Check the advanced section of
+  the documentation for details.
+
 ## [v0.4.0] - 2018-04-09
 
 ### Added

Diff for: Cargo.toml

@@ -7,8 +7,16 @@ keywords = ["arm", "cortex-m", "runtime", "startup"]
 license = "MIT OR Apache-2.0"
 name = "cortex-m-rt"
 repository = "https://github.com/japaric/cortex-m-rt"
-version = "0.4.0"
+version = "0.5.0"
+
+[build-dependencies]
+cc = "1.0.10"
 
 [dependencies]
-cortex-m = "0.3.0"
-r0 = "0.2.1"
+r0 = "0.2.1"
+
+[dev-dependencies]
+panic-semihosting = "0.2.0"
+
+[features]
+device = []

Diff for: asm.s

@@ -0,0 +1,5 @@
+  .global HardFault
+  .thumb_func
+HardFault:
+  mrs r0, MSP
+  bl UserHardFault

Diff for: bors.toml

@@ -0,0 +1,3 @@
+status = [
+  "continuous-integration/travis-ci/push",
+]

Diff for: build.rs

@@ -1,3 +1,5 @@
+extern crate cc;
+
 use std::env;
 use std::fs::File;
 use std::io::Write;
@@ -7,14 +9,48 @@ fn main() {
     let target = env::var("TARGET").unwrap();
 
     has_fpu(&target);
-    is_armv6m(&target);
+    let is_armv6m = is_armv6m(&target);
+
+    if target.starts_with("thumbv") {
+        cc::Build::new().file("asm.s").compile("asm");
+    }
 
     // Put the linker script somewhere the linker can find it
     let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
-    File::create(out.join("link.x"))
-        .unwrap()
-        .write_all(include_bytes!("link.x"))
-        .unwrap();
+    let link_x = include_bytes!("link.x.in");
+    let mut f = if env::var_os("CARGO_FEATURE_DEVICE").is_some() {
+        let mut f = File::create(out.join("link.x")).unwrap();
+
+        writeln!(
+            f,
+            r#"
+/* Provides weak aliases (cf. PROVIDED) for device specific interrupt handlers */
+/* This will usually be provided by a device crate generated using svd2rust (see `device.x`) */
+INCLUDE device.x"#
+        ).unwrap();
+        f.write_all(link_x).unwrap();
+        f
+    } else {
+        let mut f = File::create(out.join("link.x")).unwrap();
+        f.write_all(link_x).unwrap();
+        f
+    };
+
+    let max_int_handlers = if is_armv6m { 32 } else { 240 };
+
+    // checking the size of the interrupts portion of the vector table is sub-architecture dependent
+    writeln!(
+        f,
+        r#"
+ASSERT(__einterrupts - __eexceptions <= 0x{:x}, "
+There can't be more than {} interrupt handlers. This may be a bug in
+your device crate, or you may have registered more than 240 interrupt
+handlers.");
+"#,
+        max_int_handlers * 4,
+        max_int_handlers
+    ).unwrap();
+
     println!("cargo:rustc-link-search={}", out.display());
 
     println!("cargo:rerun-if-changed=build.rs");
@@ -27,8 +63,11 @@ fn has_fpu(target: &str) {
     }
 }
 
-fn is_armv6m(target: &str) {
+fn is_armv6m(target: &str) -> bool {
     if target.starts_with("thumbv6m-") {
         println!("cargo:rustc-cfg=armv6m");
+        true
+    } else {
+        false
     }
 }

Diff for: ci/install.sh

@@ -0,0 +1,9 @@
+set -euxo pipefail
+
+main() {
+    if [ $TARGET != x86_64-unknown-linux-gnu ]; then
+        rustup target add $TARGET
+    fi
+}
+
+main

Diff for: ci/script.sh

@@ -0,0 +1,34 @@
+set -euxo pipefail
+
+main() {
+    cargo check --target $TARGET
+
+    cargo check --target $TARGET --features device
+
+    local examples=(
+        minimal
+        main
+        state
+    )
+    if [ $TRAVIS_RUST_VERSION = nightly ]; then
+        for ex in "${examples[@]}"; do
+            cargo rustc --target $TARGET --example $ex -- \
+                  -C link-arg=-nostartfiles \
+                  -C link-arg=-Wl,-Tlink.x
+
+            cargo rustc --target $TARGET --example $ex --release -- \
+                  -C link-arg=-nostartfiles \
+                  -C link-arg=-Wl,-Tlink.x
+        done
+
+        cargo rustc --target $TARGET --example device --features device -- \
+              -C link-arg=-nostartfiles \
+              -C link-arg=-Wl,-Tlink.x
+
+        cargo rustc --target $TARGET --example device --features device --release -- \
+              -C link-arg=-nostartfiles \
+              -C link-arg=-Wl,-Tlink.x
+    fi
+}
+
+main

Diff for: device.x

@@ -0,0 +1,3 @@
+/* Sample device.x file */
+PROVIDE(WWDG = DefaultHandler);
+PROVIDE(PVD = DefaultHandler);

Diff for: examples/device.rs

@@ -0,0 +1,50 @@
+//! Manually create the interrupts portion of the vector table
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+#[macro_use(entry, exception)]
+extern crate cortex_m_rt as rt;
+extern crate panic_semihosting;
+
+use rt::ExceptionFrame;
+
+// the program entry point
+entry!(main);
+
+fn main() -> ! {
+    loop {}
+}
+
+// the hard fault handler
+exception!(HardFault, hard_fault);
+
+fn hard_fault(_ef: &ExceptionFrame) -> ! {
+    loop {}
+}
+
+// the default exception handler
+exception!(*, default_handler);
+
+fn default_handler(_irqn: i16) {}
+
+// interrupts portion of the vector table
+pub union Vector {
+    handler: unsafe extern "C" fn(),
+    reserved: usize,
+}
+
+extern "C" {
+    fn WWDG();
+    fn PVD();
+}
+
+#[link_section = ".vector_table.interrupts"]
+#[no_mangle]
+pub static __INTERRUPTS: [Vector; 3] = [
+    Vector { handler: WWDG },
+    Vector { reserved: 0 },
+    Vector { handler: PVD },
+];

Diff for: examples/main.rs

@@ -0,0 +1,28 @@
+//! Directly plug a `main` symbol instead of using `entry!`
+
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+#[macro_use(exception)]
+extern crate cortex_m_rt as rt;
+extern crate panic_semihosting;
+
+use rt::ExceptionFrame;
+
+#[no_mangle]
+pub unsafe extern "C" fn main() -> ! {
+    loop {}
+}
+
+// the hard fault handler
+exception!(HardFault, hard_fault);
+
+fn hard_fault(_ef: &ExceptionFrame) -> ! {
+    loop {}
+}
+
+// the default exception handler
+exception!(*, default_handler);
+
+fn default_handler(_irqn: i16) {}

Diff for: examples/minimal.rs

@@ -0,0 +1,31 @@
+//! Minimal `cortex-m-rt` based program
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+#[macro_use(entry, exception)]
+extern crate cortex_m_rt as rt;
+extern crate panic_semihosting;
+
+use rt::ExceptionFrame;
+
+// the program entry point
+entry!(main);
+
+fn main() -> ! {
+    loop {}
+}
+
+// the hard fault handler
+exception!(HardFault, hard_fault);
+
+fn hard_fault(_ef: &ExceptionFrame) -> ! {
+    loop {}
+}
+
+// the default exception handler
+exception!(*, default_handler);
+
+fn default_handler(_irqn: i16) {}