Document critical-section-single-core feature.

Author: Dirbaio

src/lib.rs

@@ -9,6 +9,14 @@
 //!
 //! # Optional features
 //!
+//! ## `critical-section-single-core`
+//!
+//! This feature enables a [`critical-section`](https://github.com/rust-embedded/critical-section)
+//! implementation suitable for single-core targets, based on disabling interrupt globally.
+//!
+//! It is **unsound** to enable it on multi-core targets. You should use a target-specific
+//! implementation that synchronizes all cores instead, typically provided by the HAL crate.
+//!
 //! ## `cm7-r0p1`
 //!
 //! This feature enables workarounds for errata found on Cortex-M7 chips with revision r0p1. Some