[Discussion] Read and Ignore traits for blocking SPI operations

[austinglaser]

Currently, there are the blocking::spi::Transfer and blocking::spi::Write traits. However, there times when one might want to read data out of a slave, without caring about what gets transmitted -- a blocking::spi::Read

This could be done with the blocking::spi::Transfer trait, but a separate trait provides two advantages:

• No need to allocate a dummy buffer to pass in as words
• An implementer of blocking::spi::Read could allow the MOSI pin to be optional

Going even further, there are times when a driver simply requires some clock cycles on the bus -- but will not be shifting meaningful data either in or out. This may seem like a corner case, but I've encountered this exact situation when configuring an ice40 FPGA. For reference, see page 19 of the programming and configuration manual. It's also a requirement for some commodity SPI flash devices.

This could be served by a blocking::spi::Ignore trait, which just takes a number of bytes to ignore.

[ryankurte]

If the chip select component was split out / explicit this would also allow the combination of write and read operations in a single transaction (ie. assert chip select, write command + address, read values, de-assert chip select), which I think is an elegant approach to resolving some difficulty allocating statically sized arrays for operations with two components (setup+write, setup+read).

[ryankurte]

This was discussed in #178 (comment) (note that this was closed in favour of #191 with only the SPI component), with the conclusion that Ignore is equivalent to Write and Read is equivalent to Transfer with a zeroed array which is preferable as it matches the physical implementation on the device.

Unless there is something else outstanding I believe that resolves this issue?