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1 parent 8f01856 commit f42b9e0Copy full SHA for f42b9e0
src/float/div.rs
@@ -454,10 +454,12 @@ intrinsics! {
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div64(a, b)
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}
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+ #[cfg(target_arch = "arm")]
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pub extern "C" fn __divsf3vfp(a: f32, b: f32) -> f32 {
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a / b
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pub extern "C" fn __divdf3vfp(a: f64, b: f64) -> f64 {
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src/float/mul.rs
@@ -189,10 +189,12 @@ intrinsics! {
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mul(a, b)
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pub extern "C" fn __mulsf3vfp(a: f32, b: f32) -> f32 {
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a * b
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pub extern "C" fn __muldf3vfp(a: f64, b: f64) -> f64 {
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