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Commit 185cc5f

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committedOct 2, 2017
Auto merge of #44885 - lu-zero:master, r=alexcrichton
More Altivec Intrinsics Float-specific intrinsics
2 parents 0f0f5db + 7bdf013 commit 185cc5f

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‎src/etc/platform-intrinsics/powerpc.json

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@@ -219,6 +219,76 @@
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"llvm": "vsumsws",
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"ret": "s32",
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"args": ["0", "0"]
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},
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{
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"intrinsic": "madd",
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"width": [128],
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"llvm": "vmaddfp",
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"ret": "f32",
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"args": ["0", "0", "0"]
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},
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{
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"intrinsic": "nmsub",
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"width": [128],
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"llvm": "vnmsubfp",
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"ret": "f32",
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"args": ["0", "0", "0"]
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},
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{
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"intrinsic": "expte",
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"width": [128],
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"llvm": "vexptefp",
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"ret": "f32",
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"args": ["0"]
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},
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{
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"intrinsic": "floor",
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"width": [128],
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"llvm": "vrfim",
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"ret": "f32",
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"args": ["0"]
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},
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{
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"intrinsic": "ceil",
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"width": [128],
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"llvm": "vrfip",
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"ret": "f32",
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"args": ["0"]
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},
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{
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"intrinsic": "round",
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"width": [128],
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"llvm": "vrfin",
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"ret": "f32",
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"args": ["0"]
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},
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{
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"intrinsic": "trunc",
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"width": [128],
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"llvm": "vrfiz",
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"ret": "f32",
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"args": ["0"]
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},
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{
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"intrinsic": "loge",
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"width": [128],
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"llvm": "vlogefp",
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"ret": "f32",
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"args": ["0"]
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},
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{
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"intrinsic": "re",
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"width": [128],
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"llvm": "vrefp",
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"ret": "f32",
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"args": ["0"]
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},
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{
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"intrinsic": "rsqrte",
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"width": [128],
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"llvm": "vrsqrtefp",
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"ret": "f32",
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"args": ["0"]
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}
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]
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}

‎src/librustc_platform_intrinsics/powerpc.rs

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@@ -397,6 +397,56 @@ pub fn find(name: &str) -> Option<Intrinsic> {
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output: &::I32x4,
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definition: Named("llvm.ppc.altivec.vsumsws")
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},
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"_vec_madd" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &INPUTS },
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output: &::F32x4,
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definition: Named("llvm.ppc.altivec.vmaddfp")
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},
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"_vec_nmsub" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &INPUTS },
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output: &::F32x4,
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definition: Named("llvm.ppc.altivec.vnmsubfp")
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},
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"_vec_expte" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
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output: &::F32x4,
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definition: Named("llvm.ppc.altivec.vexptefp")
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},
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"_vec_floor" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
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output: &::F32x4,
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definition: Named("llvm.ppc.altivec.vrfim")
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},
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"_vec_ceil" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
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output: &::F32x4,
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definition: Named("llvm.ppc.altivec.vrfip")
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},
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"_vec_round" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
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output: &::F32x4,
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definition: Named("llvm.ppc.altivec.vrfin")
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},
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"_vec_trunc" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
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output: &::F32x4,
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definition: Named("llvm.ppc.altivec.vrfiz")
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},
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"_vec_loge" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
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output: &::F32x4,
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definition: Named("llvm.ppc.altivec.vlogefp")
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},
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"_vec_re" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
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output: &::F32x4,
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definition: Named("llvm.ppc.altivec.vrefp")
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},
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"_vec_rsqrte" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
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output: &::F32x4,
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definition: Named("llvm.ppc.altivec.vrsqrtefp")
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},
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_ => return None,
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})
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}

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