Rollup merge of #126849 - workingjubilee:correctly-classify-arm-low-d…

…regs, r=Amanieu

Fix 32-bit Arm reg classes by hierarchically sorting them

We were rejecting legal `asm!` because we were asking for the "greatest" feature that includes a register class, instead of the "least" feature that includes a register class. This was only revealed on certain 32-bit Arm targets because not all have the same register limitations.

This is a somewhat hacky solution, but other solutions would require potentially rearchitecting how the internals of parsing or rejecting register classes work for all targets.

Fixes #126797

r​? ``@Amanieu``

compiler/rustc_target/src/asm/arm.rs

@@ -148,22 +148,22 @@ def_regs! {
  r11: reg = ["r11", "fp"] % frame_pointer_r11,
  r12: reg = ["r12", "ip"] % not_thumb1,
  r14: reg = ["r14", "lr"] % not_thumb1,
- s0: sreg, sreg_low16 = ["s0"],
- s1: sreg, sreg_low16 = ["s1"],
- s2: sreg, sreg_low16 = ["s2"],
- s3: sreg, sreg_low16 = ["s3"],
- s4: sreg, sreg_low16 = ["s4"],
- s5: sreg, sreg_low16 = ["s5"],
- s6: sreg, sreg_low16 = ["s6"],
- s7: sreg, sreg_low16 = ["s7"],
- s8: sreg, sreg_low16 = ["s8"],
- s9: sreg, sreg_low16 = ["s9"],
- s10: sreg, sreg_low16 = ["s10"],
- s11: sreg, sreg_low16 = ["s11"],
- s12: sreg, sreg_low16 = ["s12"],
- s13: sreg, sreg_low16 = ["s13"],
- s14: sreg, sreg_low16 = ["s14"],
- s15: sreg, sreg_low16 = ["s15"],
+ s0: sreg_low16, sreg = ["s0"],
+ s1: sreg_low16, sreg = ["s1"],
+ s2: sreg_low16, sreg = ["s2"],
+ s3: sreg_low16, sreg = ["s3"],
+ s4: sreg_low16, sreg = ["s4"],
+ s5: sreg_low16, sreg = ["s5"],
+ s6: sreg_low16, sreg = ["s6"],
+ s7: sreg_low16, sreg = ["s7"],
+ s8: sreg_low16, sreg = ["s8"],
+ s9: sreg_low16, sreg = ["s9"],
+ s10: sreg_low16, sreg = ["s10"],
+ s11: sreg_low16, sreg = ["s11"],
+ s12: sreg_low16, sreg = ["s12"],
+ s13: sreg_low16, sreg = ["s13"],
+ s14: sreg_low16, sreg = ["s14"],
+ s15: sreg_low16, sreg = ["s15"],
  s16: sreg = ["s16"],
  s17: sreg = ["s17"],
  s18: sreg = ["s18"],
@@ -180,22 +180,22 @@ def_regs! {
  s29: sreg = ["s29"],
  s30: sreg = ["s30"],
  s31: sreg = ["s31"],
- d0: dreg, dreg_low16, dreg_low8 = ["d0"],
- d1: dreg, dreg_low16, dreg_low8 = ["d1"],
- d2: dreg, dreg_low16, dreg_low8 = ["d2"],
- d3: dreg, dreg_low16, dreg_low8 = ["d3"],
- d4: dreg, dreg_low16, dreg_low8 = ["d4"],
- d5: dreg, dreg_low16, dreg_low8 = ["d5"],
- d6: dreg, dreg_low16, dreg_low8 = ["d6"],
- d7: dreg, dreg_low16, dreg_low8 = ["d7"],
- d8: dreg, dreg_low16 = ["d8"],
- d9: dreg, dreg_low16 = ["d9"],
- d10: dreg, dreg_low16 = ["d10"],
- d11: dreg, dreg_low16 = ["d11"],
- d12: dreg, dreg_low16 = ["d12"],
- d13: dreg, dreg_low16 = ["d13"],
- d14: dreg, dreg_low16 = ["d14"],
- d15: dreg, dreg_low16 = ["d15"],
+ d0: dreg_low8, dreg_low16, dreg = ["d0"],
+ d1: dreg_low8, dreg_low16, dreg = ["d1"],
+ d2: dreg_low8, dreg_low16, dreg = ["d2"],
+ d3: dreg_low8, dreg_low16, dreg = ["d3"],
+ d4: dreg_low8, dreg_low16, dreg = ["d4"],
+ d5: dreg_low8, dreg_low16, dreg = ["d5"],
+ d6: dreg_low8, dreg_low16, dreg = ["d6"],
+ d7: dreg_low8, dreg_low16, dreg = ["d7"],
+ d8: dreg_low16, dreg = ["d8"],
+ d9: dreg_low16, dreg = ["d9"],
+ d10: dreg_low16, dreg = ["d10"],
+ d11: dreg_low16, dreg = ["d11"],
+ d12: dreg_low16, dreg = ["d12"],
+ d13: dreg_low16, dreg = ["d13"],
+ d14: dreg_low16, dreg = ["d14"],
+ d15: dreg_low16, dreg = ["d15"],
  d16: dreg = ["d16"],
  d17: dreg = ["d17"],
  d18: dreg = ["d18"],
@@ -212,14 +212,14 @@ def_regs! {
  d29: dreg = ["d29"],
  d30: dreg = ["d30"],
  d31: dreg = ["d31"],
- q0: qreg, qreg_low8, qreg_low4 = ["q0"],
- q1: qreg, qreg_low8, qreg_low4 = ["q1"],
- q2: qreg, qreg_low8, qreg_low4 = ["q2"],
- q3: qreg, qreg_low8, qreg_low4 = ["q3"],
- q4: qreg, qreg_low8 = ["q4"],
- q5: qreg, qreg_low8 = ["q5"],
- q6: qreg, qreg_low8 = ["q6"],
- q7: qreg, qreg_low8 = ["q7"],
+ q0: qreg_low4, qreg_low8, qreg = ["q0"],
+ q1: qreg_low4, qreg_low8, qreg = ["q1"],
+ q2: qreg_low4, qreg_low8, qreg = ["q2"],
+ q3: qreg_low4, qreg_low8, qreg = ["q3"],
+ q4: qreg_low8, qreg = ["q4"],
+ q5: qreg_low8, qreg = ["q5"],
+ q6: qreg_low8, qreg = ["q6"],
+ q7: qreg_low8, qreg = ["q7"],
  q8: qreg = ["q8"],
  q9: qreg = ["q9"],
  q10: qreg = ["q10"],

tests/ui/asm/arm-low-dreg.rs

@@ -0,0 +1,33 @@
+//@ build-pass
+//@ compile-flags: --target=armv7-unknown-linux-gnueabihf
+//@ needs-llvm-components: arm
+#![feature(no_core, rustc_attrs, decl_macro, lang_items)]
+#![crate_type = "rlib"]
+#![no_std]
+#![no_core]
+
+// We accidentally classified "d0"..="d15" as dregs, even though they are in dreg_low16,
+// and thus didn't compile them on platforms with only 16 dregs.
+// Highlighted in https://github.com/rust-lang/rust/issues/126797
+
+#[lang = "sized"]
+trait Sized {}
+
+#[lang = "copy"]
+trait Copy {}
+
+impl Copy for f64 {}
+
+#[rustc_builtin_macro]
+pub macro asm("assembly template", $(operands,)* $(options($(option),*))?) {
+ /* compiler built-in */
+}
+
+
+fn f(x: f64) -> f64 {
+ let out: f64;
+ unsafe {
+ asm!("vmov.f64 d1, d0", out("d1") out, in("d0") x);
+ }
+ out
+}