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Auto merge of #73511 - Manishearth:rollup-3iffxd8, r=Manishearth
Rollup of 13 pull requests
Successful merges:
- #71568 (Document unsafety in slice/sort.rs)
- #72709 (`#[deny(unsafe_op_in_unsafe_fn)]` in liballoc)
- #73214 (Add asm!() support for hexagon)
- #73248 (save_analysis: improve handling of enum struct variant)
- #73257 (ty: projections in `transparent_newtype_field`)
- #73261 (Suggest `?Sized` when applicable for ADTs)
- #73300 (Implement crate-level-only lints checking.)
- #73334 (Note numeric literals that can never fit in an expected type)
- #73357 (Use `LocalDefId` for import IDs in trait map)
- #73364 (asm: Allow multiple template string arguments; interpret them as newline-separated)
- #73382 (Only display other method receiver candidates if they actually apply)
- #73465 (Add specialization of `ToString for char`)
- #73489 (Refactor hir::Place)
Failed merges:
r? @ghost
The macro will initially be supported only on ARM, AArch64, x86, x86-64 and RISC-V targets. Support for more targets may be added in the future. The compiler will emit an error if `asm!` is used on an unsupported target.
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The macro will initially be supported only on ARM, AArch64, Hexagon, x86, x86-64 and RISC-V targets. Support for more targets may be added in the future. The compiler will emit an error if `asm!` is used on an unsupported target.
The assembler template uses the same syntax as [format strings][format-syntax] (i.e. placeholders are specified by curly braces). The corresponding arguments are accessed in order, by index, or by name. However, implicit named arguments (introduced by [RFC #2795][rfc-2795]) are not supported.
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An `asm!` invocation may have one or more template string arguments; an `asm!` with multiple template string arguments is treated as if all the strings were concatenated with a `\n` between them. The expected usage is for each template string argument to correspond to a line of assembly code. All template string arguments must appear before any other arguments.
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As with format strings, named arguments must appear after positional arguments. Explicit register operands must appear at the end of the operand list, after named arguments if any.
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Explicit register operands cannot be used by placeholders in the template string. All other named and positional operands must appear at least once in the template string, otherwise a compiler error is generated.
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The exact assembly code syntax is target-specific and opaque to the compiler except for the way operands are substituted into the template string to form the code passed to the assembler.
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The 4 targets specified in this RFC (x86, ARM, AArch64, RISC-V) all use the assembly code syntax of the GNU assembler (GAS). On x86, the `.intel_syntax noprefix` mode of GAS is used by default. On ARM, the `.syntax unified` mode is used. These targets impose an additional restriction on the assembly code: any assembler state (e.g. the current section which can be changed with `.section`) must be restored to its original value at the end of the asm string. Assembly code that does not conform to the GAS syntax will result in assembler-specific behavior.
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The 5 targets specified in this RFC (x86, ARM, AArch64, RISC-V, Hexagon) all use the assembly code syntax of the GNU assembler (GAS). On x86, the `.intel_syntax noprefix` mode of GAS is used by default. On ARM, the `.syntax unified` mode is used. These targets impose an additional restriction on the assembly code: any assembler state (e.g. the current section which can be changed with `.section`) must be restored to its original value at the end of the asm string. Assembly code that does not conform to the GAS syntax will result in assembler-specific behavior.
> **Note**: On x86 we treat `reg_byte` differently from `reg` because the compiler can allocate `al` and `ah` separately whereas `reg` reserves the whole register.
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@@ -509,6 +525,7 @@ Each register class has constraints on which value types they can be used with.
> **Note**: For the purposes of the above table pointers, function pointers and `isize`/`usize` are treated as the equivalent integer type (`i16`/`i32`/`i64` depending on the target).
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@@ -565,13 +582,16 @@ Some registers have multiple names. These are all treated by the compiler as ide
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| RISC-V |`f[10-17]`|`fa[0-7]`|
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| RISC-V |`f[18-27]`|`fs[2-11]`|
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| RISC-V |`f[28-31]`|`ft[8-11]`|
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| Hexagon |`r29`|`sp`|
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| Hexagon |`r30`|`fr`|
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| Hexagon |`r31`|`lr`|
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Some registers cannot be used for input or output operands:
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| Architecture | Unsupported register | Reason |
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| ------------ | -------------------- | ------ |
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| All |`sp`| The stack pointer must be restored to its original value at the end of an asm code block. |
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| All |`bp` (x86), `r11` (ARM), `x29` (AArch64), `x8` (RISC-V) | The frame pointer cannot be used as an input or output. |
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| All |`bp` (x86), `r11` (ARM), `x29` (AArch64), `x8` (RISC-V), `fr` (Hexagon)| The frame pointer cannot be used as an input or output. |
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| x86 |`k0`| This is a constant zero register which can't be modified. |
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| x86 |`ip`| This is the program counter, not a real register. |
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| x86 |`mm[0-7]`| MMX registers are not currently supported (but may be in the future). |
@@ -580,6 +600,7 @@ Some registers cannot be used for input or output operands:
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| ARM |`pc`| This is the program counter, not a real register. |
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| RISC-V |`x0`| This is a constant zero register which can't be modified. |
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| RISC-V |`gp`, `tp`| These registers are reserved and cannot be used as inputs or outputs. |
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| Hexagon |`lr`| This is the link register which cannot be used as an input or output. |
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## Template modifiers
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@@ -625,6 +646,7 @@ The supported modifiers are a subset of LLVM's (and GCC's) [asm template argumen
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| NVPTX |`reg64`| None |`rd0`| None |
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| RISC-V |`reg`| None |`x1`| None |
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| RISC-V |`freg`| None |`f0`| None |
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| Hexagon |`reg`| None |`r0`| None |
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> Notes:
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> - on ARM `e` / `f`: this prints the low or high doubleword register name of a NEON quad (128-bit) register.
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