Always specify llvm_abiname for RISC-V targets

rust-lang · Oct 17, 2024 · 3ea91c0 · 3ea91c0
1 parent 7342830
commit 3ea91c0
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Showing 16 changed files with 71 additions and 1 deletion.
diff --git a/compiler/rustc_target/src/spec/targets/riscv32i_unknown_none_elf.rs b/compiler/rustc_target/src/spec/targets/riscv32i_unknown_none_elf.rs
@@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
  max_atomic_width: Some(32),
  atomic_cas: false,
  features: "+forced-atomics".into(),
+ llvm_abiname: "ilp32".into(),
  panic_strategy: PanicStrategy::Abort,
  relocation_model: RelocModel::Static,
  emit_debug_gdb_scripts: false,

diff --git a/compiler/rustc_target/src/spec/targets/riscv32im_risc0_zkvm_elf.rs b/compiler/rustc_target/src/spec/targets/riscv32im_risc0_zkvm_elf.rs
@@ -29,6 +29,7 @@ pub(crate) fn target() -> Target {
  atomic_cas: true,
 
  features: "+m".into(),
+ llvm_abiname: "ilp32".into(),
  executables: true,
  panic_strategy: PanicStrategy::Abort,
  relocation_model: RelocModel::Static,

diff --git a/compiler/rustc_target/src/spec/targets/riscv32im_unknown_none_elf.rs b/compiler/rustc_target/src/spec/targets/riscv32im_unknown_none_elf.rs
@@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
  max_atomic_width: Some(32),
  atomic_cas: false,
  features: "+m,+forced-atomics".into(),
+ llvm_abiname: "ilp32".into(),
  panic_strategy: PanicStrategy::Abort,
  relocation_model: RelocModel::Static,
  emit_debug_gdb_scripts: false,

diff --git a/compiler/rustc_target/src/spec/targets/riscv32ima_unknown_none_elf.rs b/compiler/rustc_target/src/spec/targets/riscv32ima_unknown_none_elf.rs
@@ -19,6 +19,7 @@ pub(crate) fn target() -> Target {
  cpu: "generic-rv32".into(),
  max_atomic_width: Some(32),
  features: "+m,+a".into(),
+ llvm_abiname: "ilp32".into(),
  panic_strategy: PanicStrategy::Abort,
  relocation_model: RelocModel::Static,
  emit_debug_gdb_scripts: false,

diff --git a/compiler/rustc_target/src/spec/targets/riscv32imac_esp_espidf.rs b/compiler/rustc_target/src/spec/targets/riscv32imac_esp_espidf.rs
@@ -27,6 +27,7 @@ pub(crate) fn target() -> Target {
  atomic_cas: true,
 
  features: "+m,+a,+c".into(),
+ llvm_abiname: "ilp32".into(),
  panic_strategy: PanicStrategy::Abort,
  relocation_model: RelocModel::Static,
  emit_debug_gdb_scripts: false,

diff --git a/compiler/rustc_target/src/spec/targets/riscv32imac_unknown_none_elf.rs b/compiler/rustc_target/src/spec/targets/riscv32imac_unknown_none_elf.rs
@@ -19,6 +19,7 @@ pub(crate) fn target() -> Target {
  cpu: "generic-rv32".into(),
  max_atomic_width: Some(32),
  features: "+m,+a,+c".into(),
+ llvm_abiname: "ilp32".into(),
  panic_strategy: PanicStrategy::Abort,
  relocation_model: RelocModel::Static,
  emit_debug_gdb_scripts: false,

diff --git a/compiler/rustc_target/src/spec/targets/riscv32imac_unknown_nuttx_elf.rs b/compiler/rustc_target/src/spec/targets/riscv32imac_unknown_nuttx_elf.rs
@@ -21,6 +21,7 @@ pub(crate) fn target() -> Target {
  cpu: "generic-rv32".into(),
  max_atomic_width: Some(32),
  features: "+m,+a,+c".into(),
+ llvm_abiname: "ilp32".into(),
  panic_strategy: PanicStrategy::Unwind,
  relocation_model: RelocModel::Static,
  ..Default::default()

diff --git a/compiler/rustc_target/src/spec/targets/riscv32imac_unknown_xous_elf.rs b/compiler/rustc_target/src/spec/targets/riscv32imac_unknown_xous_elf.rs
@@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
  cpu: "generic-rv32".into(),
  max_atomic_width: Some(32),
  features: "+m,+a,+c".into(),
+ llvm_abiname: "ilp32".into(),
  panic_strategy: PanicStrategy::Unwind,
  relocation_model: RelocModel::Static,
  ..Default::default()

diff --git a/compiler/rustc_target/src/spec/targets/riscv32imc_esp_espidf.rs b/compiler/rustc_target/src/spec/targets/riscv32imc_esp_espidf.rs
@@ -30,6 +30,7 @@ pub(crate) fn target() -> Target {
  atomic_cas: true,
 
  features: "+m,+c".into(),
+ llvm_abiname: "ilp32".into(),
  panic_strategy: PanicStrategy::Abort,
  relocation_model: RelocModel::Static,
  emit_debug_gdb_scripts: false,

diff --git a/compiler/rustc_target/src/spec/targets/riscv32imc_unknown_none_elf.rs b/compiler/rustc_target/src/spec/targets/riscv32imc_unknown_none_elf.rs
@@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
  max_atomic_width: Some(32),
  atomic_cas: false,
  features: "+m,+c,+forced-atomics".into(),
+ llvm_abiname: "ilp32".into(),
  panic_strategy: PanicStrategy::Abort,
  relocation_model: RelocModel::Static,
  emit_debug_gdb_scripts: false,

diff --git a/compiler/rustc_target/src/spec/targets/riscv32imc_unknown_nuttx_elf.rs b/compiler/rustc_target/src/spec/targets/riscv32imc_unknown_nuttx_elf.rs
@@ -21,6 +21,7 @@ pub(crate) fn target() -> Target {
  cpu: "generic-rv32".into(),
  max_atomic_width: Some(32),
  features: "+m,+c".into(),
+ llvm_abiname: "ilp32".into(),
  panic_strategy: PanicStrategy::Unwind,
  relocation_model: RelocModel::Static,
  ..Default::default()

diff --git a/compiler/rustc_target/src/spec/targets/riscv64imac_unknown_none_elf.rs b/compiler/rustc_target/src/spec/targets/riscv64imac_unknown_none_elf.rs
@@ -22,6 +22,7 @@ pub(crate) fn target() -> Target {
  cpu: "generic-rv64".into(),
  max_atomic_width: Some(64),
  features: "+m,+a,+c".into(),
+ llvm_abiname: "lp64".into(),
  panic_strategy: PanicStrategy::Abort,
  relocation_model: RelocModel::Static,
  code_model: Some(CodeModel::Medium),

diff --git a/compiler/rustc_target/src/spec/targets/riscv64imac_unknown_nuttx_elf.rs b/compiler/rustc_target/src/spec/targets/riscv64imac_unknown_nuttx_elf.rs
@@ -24,6 +24,7 @@ pub(crate) fn target() -> Target {
  cpu: "generic-rv64".into(),
  max_atomic_width: Some(64),
  features: "+m,+a,+c".into(),
+ llvm_abiname: "lp64".into(),
  panic_strategy: PanicStrategy::Abort,
  relocation_model: RelocModel::Static,
  code_model: Some(CodeModel::Medium),

diff --git a/compiler/rustc_target/src/spec/tests/tests_impl.rs b/compiler/rustc_target/src/spec/tests/tests_impl.rs
@@ -152,6 +152,17 @@ impl Target {
  if self.crt_static_default || self.crt_static_allows_dylibs {
  assert!(self.crt_static_respected);
  }
+
+ // Check that RISC-V targets always specify which ABI they use.
+ match &*self.arch {
+ "riscv32" => {
+ assert_matches!(&*self.llvm_abiname, "ilp32" | "ilp32f" | "ilp32d" | "ilp32e")
+ }
+ "riscv64" => {
+ assert_matches!(&*self.llvm_abiname, "lp64" | "lp64f" | "lp64d" | "lp64q")
+ }
+ _ => {}
+ }
  }
 
  // Add your target to the whitelist if it has `std` library

diff --git a/tests/assembly/riscv-soft-abi-with-float-features.rs b/tests/assembly/riscv-soft-abi-with-float-features.rs
@@ -0,0 +1,46 @@
+//@ assembly-output: emit-asm
+//@ compile-flags: --target riscv64imac-unknown-none-elf -Ctarget-feature=+f,+d
+//@ needs-llvm-components: riscv
+
+#![feature(no_core, lang_items, f16)]
+#![crate_type = "lib"]
+#![no_core]
+
+#[lang = "sized"]
+trait Sized {}
+
+#[lang = "copy"]
+trait Copy {}
+
+impl Copy for f16 {}
+impl Copy for f32 {}
+impl Copy for f64 {}
+
+// This test checks that the floats are all returned in `a0` as required by the `lp64` ABI.
+
+// CHECK-LABEL: read_f16
+#[no_mangle]
+pub extern "C" fn read_f16(x: &f16) -> f16 {
+ // CHECK: lh a0, 0(a0)
+ // CHECK-NEXT: lui a1, 1048560
+ // CHECK-NEXT: or a0, a0, a1
+ // CHECK-NEXT: ret
+ *x
+}
+
+// CHECK-LABEL: read_f32
+#[no_mangle]
+pub extern "C" fn read_f32(x: &f32) -> f32 {
+ // CHECK: flw fa5, 0(a0)
+ // CHECK-NEXT: fmv.x.w a0, fa5
+ // CHECK-NEXT: ret
+ *x
+}
+
+// CHECK-LABEL: read_f64
+#[no_mangle]
+pub extern "C" fn read_f64(x: &f64) -> f64 {
+ // CHECK: ld a0, 0(a0)
+ // CHECK-NEXT: ret
+ *x
+}
diff --git a/tests/codegen/riscv-target-abi.rs b/tests/codegen/riscv-target-abi.rs
@@ -10,7 +10,7 @@
 
 //@[riscv32imac] compile-flags: --target=riscv32imac-unknown-none-elf
 //@[riscv32imac] needs-llvm-components: riscv
-// riscv32imac-NOT: !"target-abi"
+// riscv32imac: !{i32 1, !"target-abi", !"ilp32"}
 
 #![feature(no_core, lang_items)]
 #![crate_type = "lib"]