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Auto merge of #77272 - jonas-schievink:rollup-dydo5kn, r=jonas-schievink
Rollup of 7 pull requests Successful merges: - #76839 (Add asm! support for MIPS) - #77203 (Check for missing const-stability attributes in `rustc_passes`) - #77249 (Separate `private_intra_doc_links` and `broken_intra_doc_links` into separate lints) - #77252 (reduce overlong line) - #77256 (Fix typo in ExpnData documentation) - #77262 (Remove duplicate comment) - #77263 (Clean up trivial if let) Failed merges: r? `@ghost`
2 parents 1d216fe + 344ab3f commit 4529af9

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22 files changed

+520
-30
lines changed

22 files changed

+520
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Diff for: ‎compiler/rustc_codegen_llvm/src/asm.rs

+25
Original file line numberDiff line numberDiff line change
@@ -259,6 +259,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
259259
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
260260
InlineAsmArch::Nvptx64 => {}
261261
InlineAsmArch::Hexagon => {}
262+
InlineAsmArch::Mips => {}
262263
}
263264
}
264265
if !options.contains(InlineAsmOptions::NOMEM) {
@@ -505,6 +506,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
505506
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
506507
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
507508
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
509+
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "r",
510+
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
508511
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
509512
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
510513
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
@@ -551,6 +554,7 @@ fn modifier_to_llvm(
551554
}
552555
}
553556
InlineAsmRegClass::Hexagon(_) => None,
557+
InlineAsmRegClass::Mips(_) => None,
554558
InlineAsmRegClass::Nvptx(_) => None,
555559
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
556560
| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
@@ -603,6 +607,8 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
603607
cx.type_vector(cx.type_i64(), 2)
604608
}
605609
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
610+
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
611+
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
606612
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
607613
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
608614
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
@@ -700,6 +706,12 @@ fn llvm_fixup_input(
700706
value
701707
}
702708
}
709+
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
710+
// MIPS only supports register-length arithmetics.
711+
Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
712+
Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
713+
_ => value,
714+
},
703715
_ => value,
704716
}
705717
}
@@ -768,6 +780,13 @@ fn llvm_fixup_output(
768780
value
769781
}
770782
}
783+
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
784+
// MIPS only supports register-length arithmetics.
785+
Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
786+
Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
787+
Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
788+
_ => value,
789+
},
771790
_ => value,
772791
}
773792
}
@@ -831,6 +850,12 @@ fn llvm_fixup_output_type(
831850
layout.llvm_type(cx)
832851
}
833852
}
853+
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
854+
// MIPS only supports register-length arithmetics.
855+
Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
856+
Primitive::F32 => cx.type_i32(),
857+
_ => layout.llvm_type(cx),
858+
},
834859
_ => layout.llvm_type(cx),
835860
}
836861
}

Diff for: ‎compiler/rustc_lint/src/lib.rs

+1
Original file line numberDiff line numberDiff line change
@@ -305,6 +305,7 @@ fn register_builtins(store: &mut LintStore, no_interleave_lints: bool) {
305305
add_lint_group!(
306306
"rustdoc",
307307
BROKEN_INTRA_DOC_LINKS,
308+
PRIVATE_INTRA_DOC_LINKS,
308309
INVALID_CODEBLOCK_ATTRIBUTES,
309310
MISSING_DOC_CODE_EXAMPLES,
310311
PRIVATE_DOC_TESTS

Diff for: ‎compiler/rustc_mir/src/const_eval/fn_queries.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ pub fn is_min_const_fn(tcx: TyCtxt<'_>, def_id: DefId) -> bool {
5050
None => {
5151
if let Some(stab) = tcx.lookup_stability(def_id) {
5252
if stab.level.is_stable() {
53-
tcx.sess.span_err(
53+
tcx.sess.delay_span_bug(
5454
tcx.def_span(def_id),
5555
"stable const functions must have either `rustc_const_stable` or \
5656
`rustc_const_unstable` attribute",

Diff for: ‎compiler/rustc_mir/src/transform/check_consts/validation.rs

-3
Original file line numberDiff line numberDiff line change
@@ -204,9 +204,6 @@ impl Validator<'mir, 'tcx> {
204204
pub fn check_body(&mut self) {
205205
let ConstCx { tcx, body, def_id, .. } = *self.ccx;
206206

207-
// HACK: This function has side-effects???? Make sure we call it.
208-
let _ = crate::const_eval::is_min_const_fn(tcx, def_id.to_def_id());
209-
210207
// The local type and predicate checks are not free and only relevant for `const fn`s.
211208
if self.const_kind() == hir::ConstContext::ConstFn {
212209
// Prevent const trait methods from being annotated as `stable`.

Diff for: ‎compiler/rustc_passes/src/stability.rs

+31-7
Original file line numberDiff line numberDiff line change
@@ -459,6 +459,21 @@ impl<'tcx> MissingStabilityAnnotations<'tcx> {
459459
self.tcx.sess.span_err(span, &format!("{} has missing stability attribute", descr));
460460
}
461461
}
462+
463+
fn check_missing_const_stability(&self, hir_id: HirId, span: Span) {
464+
let stab_map = self.tcx.stability();
465+
let stab = stab_map.local_stability(hir_id);
466+
if stab.map_or(false, |stab| stab.level.is_stable()) {
467+
let const_stab = stab_map.local_const_stability(hir_id);
468+
if const_stab.is_none() {
469+
self.tcx.sess.span_err(
470+
span,
471+
"`#[stable]` const functions must also be either \
472+
`#[rustc_const_stable]` or `#[rustc_const_unstable]`",
473+
);
474+
}
475+
}
476+
}
462477
}
463478

464479
impl<'tcx> Visitor<'tcx> for MissingStabilityAnnotations<'tcx> {
@@ -469,14 +484,23 @@ impl<'tcx> Visitor<'tcx> for MissingStabilityAnnotations<'tcx> {
469484
}
470485

471486
fn visit_item(&mut self, i: &'tcx Item<'tcx>) {
472-
match i.kind {
473-
// Inherent impls and foreign modules serve only as containers for other items,
474-
// they don't have their own stability. They still can be annotated as unstable
475-
// and propagate this unstability to children, but this annotation is completely
476-
// optional. They inherit stability from their parents when unannotated.
477-
hir::ItemKind::Impl { of_trait: None, .. } | hir::ItemKind::ForeignMod(..) => {}
487+
// Inherent impls and foreign modules serve only as containers for other items,
488+
// they don't have their own stability. They still can be annotated as unstable
489+
// and propagate this unstability to children, but this annotation is completely
490+
// optional. They inherit stability from their parents when unannotated.
491+
if !matches!(
492+
i.kind,
493+
hir::ItemKind::Impl { of_trait: None, .. } | hir::ItemKind::ForeignMod(..)
494+
) {
495+
self.check_missing_stability(i.hir_id, i.span);
496+
}
478497

479-
_ => self.check_missing_stability(i.hir_id, i.span),
498+
// Ensure `const fn` that are `stable` have one of `rustc_const_unstable` or
499+
// `rustc_const_stable`.
500+
if self.tcx.features().staged_api
501+
&& matches!(&i.kind, hir::ItemKind::Fn(sig, ..) if sig.header.is_const())
502+
{
503+
self.check_missing_const_stability(i.hir_id, i.span);
480504
}
481505

482506
intravisit::walk_item(self, i)

Diff for: ‎compiler/rustc_session/src/lint/builtin.rs

+11
Original file line numberDiff line numberDiff line change
@@ -1826,6 +1826,17 @@ declare_lint! {
18261826
"failures in resolving intra-doc link targets"
18271827
}
18281828

1829+
declare_lint! {
1830+
/// This is a subset of `broken_intra_doc_links` that warns when linking from
1831+
/// a public item to a private one. This is a `rustdoc` only lint, see the
1832+
/// documentation in the [rustdoc book].
1833+
///
1834+
/// [rustdoc book]: ../../../rustdoc/lints.html#private_intra_doc_links
1835+
pub PRIVATE_INTRA_DOC_LINKS,
1836+
Warn,
1837+
"linking from a public item to a private one"
1838+
}
1839+
18291840
declare_lint! {
18301841
/// The `invalid_codeblock_attributes` lint detects code block attributes
18311842
/// in documentation examples that have potentially mis-typed values. This

Diff for: ‎compiler/rustc_session/src/session.rs

-3
Original file line numberDiff line numberDiff line change
@@ -1103,9 +1103,6 @@ impl Session {
11031103
self.used_attrs.lock().is_marked(attr)
11041104
}
11051105

1106-
/// Returns `true` if the attribute's path matches the argument. If it matches, then the
1107-
/// attribute is marked as used.
1108-
11091106
/// Returns `true` if the attribute's path matches the argument. If it
11101107
/// matches, then the attribute is marked as used.
11111108
///

Diff for: ‎compiler/rustc_span/src/hygiene.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -702,7 +702,7 @@ pub struct ExpnData {
702702
/// The `DefId` of the macro being invoked,
703703
/// if this `ExpnData` corresponds to a macro invocation
704704
pub macro_def_id: Option<DefId>,
705-
/// The crate that originally created this `ExpnData. During
705+
/// The crate that originally created this `ExpnData`. During
706706
/// metadata serialization, we only encode `ExpnData`s that were
707707
/// created locally - when our serialized metadata is decoded,
708708
/// foreign `ExpnId`s will have their `ExpnData` looked up
@@ -759,7 +759,7 @@ impl ExpnData {
759759

760760
#[inline]
761761
pub fn is_root(&self) -> bool {
762-
if let ExpnKind::Root = self.kind { true } else { false }
762+
matches!(self.kind, ExpnKind::Root)
763763
}
764764
}
765765

Diff for: ‎compiler/rustc_target/src/asm/mips.rs

+132
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,132 @@
1+
use super::{InlineAsmArch, InlineAsmType};
2+
use rustc_macros::HashStable_Generic;
3+
use std::fmt;
4+
5+
def_reg_class! {
6+
Mips MipsInlineAsmRegClass {
7+
reg,
8+
freg,
9+
}
10+
}
11+
12+
impl MipsInlineAsmRegClass {
13+
pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
14+
&[]
15+
}
16+
17+
pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
18+
None
19+
}
20+
21+
pub fn suggest_modifier(
22+
self,
23+
_arch: InlineAsmArch,
24+
_ty: InlineAsmType,
25+
) -> Option<(char, &'static str)> {
26+
None
27+
}
28+
29+
pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
30+
None
31+
}
32+
33+
pub fn supported_types(
34+
self,
35+
_arch: InlineAsmArch,
36+
) -> &'static [(InlineAsmType, Option<&'static str>)] {
37+
match self {
38+
Self::reg => types! { _: I8, I16, I32, F32; },
39+
Self::freg => types! { _: F32; },
40+
}
41+
}
42+
}
43+
44+
// The reserved registers are somewhat taken from <https://git.io/JUR1k#L150>.
45+
def_regs! {
46+
Mips MipsInlineAsmReg MipsInlineAsmRegClass {
47+
v0: reg = ["$2", "$v0"],
48+
v1: reg = ["$3", "$v1"],
49+
a0: reg = ["$4", "$a0"],
50+
a1: reg = ["$5", "$a1"],
51+
a2: reg = ["$6", "$a2"],
52+
a3: reg = ["$7", "$a3"],
53+
// FIXME: Reserve $t0, $t1 if in mips16 mode.
54+
t0: reg = ["$8", "$t0"],
55+
t1: reg = ["$9", "$t1"],
56+
t2: reg = ["$10", "$t2"],
57+
t3: reg = ["$11", "$t3"],
58+
t4: reg = ["$12", "$t4"],
59+
t5: reg = ["$13", "$t5"],
60+
t6: reg = ["$14", "$t6"],
61+
t7: reg = ["$15", "$t7"],
62+
s0: reg = ["$16", "$s0"],
63+
s1: reg = ["$17", "$s1"],
64+
s2: reg = ["$18", "$s2"],
65+
s3: reg = ["$19", "$s3"],
66+
s4: reg = ["$20", "$s4"],
67+
s5: reg = ["$21", "$s5"],
68+
s6: reg = ["$22", "$s6"],
69+
s7: reg = ["$23", "$s7"],
70+
t8: reg = ["$24", "$t8"],
71+
t9: reg = ["$25", "$t9"],
72+
f0: freg = ["$f0"],
73+
f1: freg = ["$f1"],
74+
f2: freg = ["$f2"],
75+
f3: freg = ["$f3"],
76+
f4: freg = ["$f4"],
77+
f5: freg = ["$f5"],
78+
f6: freg = ["$f6"],
79+
f7: freg = ["$f7"],
80+
f8: freg = ["$f8"],
81+
f9: freg = ["$f9"],
82+
f10: freg = ["$f10"],
83+
f11: freg = ["$f11"],
84+
f12: freg = ["$f12"],
85+
f13: freg = ["$f13"],
86+
f14: freg = ["$f14"],
87+
f15: freg = ["$f15"],
88+
f16: freg = ["$f16"],
89+
f17: freg = ["$f17"],
90+
f18: freg = ["$f18"],
91+
f19: freg = ["$f19"],
92+
f20: freg = ["$f20"],
93+
f21: freg = ["$f21"],
94+
f22: freg = ["$f22"],
95+
f23: freg = ["$f23"],
96+
f24: freg = ["$f24"],
97+
f25: freg = ["$f25"],
98+
f26: freg = ["$f26"],
99+
f27: freg = ["$f27"],
100+
f28: freg = ["$f28"],
101+
f29: freg = ["$f29"],
102+
f30: freg = ["$f30"],
103+
f31: freg = ["$f31"],
104+
#error = ["$0", "$zero"] =>
105+
"constant zero cannot be used as an operand for inline asm",
106+
#error = ["$1", "$at"] =>
107+
"reserved for assembler (Assembler Temp)",
108+
#error = ["$26", "$k0"] =>
109+
"OS-reserved register cannot be used as an operand for inline asm",
110+
#error = ["$27", "$k1"] =>
111+
"OS-reserved register cannot be used as an operand for inline asm",
112+
#error = ["$28", "$gp"] =>
113+
"the global pointer cannot be used as an operand for inline asm",
114+
#error = ["$29", "$sp"] =>
115+
"the stack pointer cannot be used as an operand for inline asm",
116+
#error = ["$30", "$s8", "$fp"] =>
117+
"the frame pointer cannot be used as an operand for inline asm",
118+
#error = ["$31", "$ra"] =>
119+
"the return address register cannot be used as an operand for inline asm",
120+
}
121+
}
122+
123+
impl MipsInlineAsmReg {
124+
pub fn emit(
125+
self,
126+
out: &mut dyn fmt::Write,
127+
_arch: InlineAsmArch,
128+
_modifier: Option<char>,
129+
) -> fmt::Result {
130+
out.write_str(self.name())
131+
}
132+
}

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