Skip to content

Commit 4d7b4a4

Browse files
MabezDevMabezDev
committed
Add riscv32 imafc bare metal target
- riscv32imac-unknown-none-elf - Add platform support docs for rv32
1 parent c225c45 commit 4d7b4a4

File tree

11 files changed

+71
-4
lines changed

11 files changed

+71
-4
lines changed

‎compiler/rustc_target/src/spec/mod.rs

+1
Original file line numberDiff line numberDiff line change
@@ -1641,6 +1641,7 @@ supported_targets! {
16411641
("riscv32imc-esp-espidf", riscv32imc_esp_espidf),
16421642
("riscv32imac-esp-espidf", riscv32imac_esp_espidf),
16431643
("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf),
1644+
("riscv32imafc-unknown-none-elf", riscv32imafc_unknown_none_elf),
16441645
("riscv32imac-unknown-xous-elf", riscv32imac_unknown_xous_elf),
16451646
("riscv32gc-unknown-linux-gnu", riscv32gc_unknown_linux_gnu),
16461647
("riscv32gc-unknown-linux-musl", riscv32gc_unknown_linux_musl),

‎compiler/rustc_target/src/spec/targets/riscv32imafc_unknown_none_elf.rs

+24
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetOptions};
2+
3+
pub fn target() -> Target {
4+
Target {
5+
data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
6+
llvm_target: "riscv32".into(),
7+
pointer_width: 32,
8+
arch: "riscv32".into(),
9+
10+
options: TargetOptions {
11+
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
12+
linker: Some("rust-lld".into()),
13+
cpu: "generic-rv32".into(),
14+
max_atomic_width: Some(32),
15+
llvm_abiname: "ilp32f".into(),
16+
features: "+m,+a,+c,+f".into(),
17+
panic_strategy: PanicStrategy::Abort,
18+
relocation_model: RelocModel::Static,
19+
emit_debug_gdb_scripts: false,
20+
eh_frame_header: false,
21+
..Default::default()
22+
},
23+
}
24+
}

‎src/ci/docker/host-x86_64/dist-various-1/Dockerfile

+1
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,7 @@ ENV TARGETS=$TARGETS,thumbv8m.main-none-eabihf
9696
ENV TARGETS=$TARGETS,riscv32i-unknown-none-elf
9797
ENV TARGETS=$TARGETS,riscv32imc-unknown-none-elf
9898
ENV TARGETS=$TARGETS,riscv32imac-unknown-none-elf
99+
ENV TARGETS=$TARGETS,riscv32imafc-unknown-none-elf
99100
ENV TARGETS=$TARGETS,riscv64imac-unknown-none-elf
100101
ENV TARGETS=$TARGETS,riscv64gc-unknown-none-elf
101102
ENV TARGETS=$TARGETS,armebv7r-none-eabi

‎src/doc/rustc/src/SUMMARY.md

+1
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@
4343
- [nvptx64-nvidia-cuda](platform-support/nvptx64-nvidia-cuda.md)
4444
- [powerpc64-ibm-aix](platform-support/aix.md)
4545
- [riscv32imac-unknown-xous-elf](platform-support/riscv32imac-unknown-xous-elf.md)
46+
- [riscv32*-unknown-none-elf](platform-support/riscv32imac-unknown-none-elf.md)
4647
- [sparc-unknown-none-elf](./platform-support/sparc-unknown-none-elf.md)
4748
- [*-pc-windows-gnullvm](platform-support/pc-windows-gnullvm.md)
4849
- [\*-nto-qnx-\*](platform-support/nto-qnx.md)

‎src/doc/rustc/src/platform-support.md

+5-4
Original file line numberDiff line numberDiff line change
@@ -160,9 +160,11 @@ target | std | notes
160160
[`loongarch64-unknown-none`](platform-support/loongarch-none.md) | * | | LoongArch64 Bare-metal (LP64D ABI)
161161
[`loongarch64-unknown-none-softfloat`](platform-support/loongarch-none.md) | * | | LoongArch64 Bare-metal (LP64S ABI)
162162
[`nvptx64-nvidia-cuda`](platform-support/nvptx64-nvidia-cuda.md) | * | --emit=asm generates PTX code that [runs on NVIDIA GPUs]
163-
`riscv32i-unknown-none-elf` | * | Bare RISC-V (RV32I ISA)
164-
`riscv32imac-unknown-none-elf` | * | Bare RISC-V (RV32IMAC ISA)
165-
`riscv32imc-unknown-none-elf` | * | Bare RISC-V (RV32IMC ISA)
163+
[`riscv32i-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32I ISA)
164+
[`riscv32imac-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMAC ISA)
165+
[`riscv32imafc-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMAFC ISA)
166+
[`riscv32im-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | | Bare RISC-V (RV32IM ISA)
167+
[`riscv32imc-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMC ISA)
166168
`riscv64gc-unknown-none-elf` | * | Bare RISC-V (RV64IMAFDC ISA)
167169
`riscv64imac-unknown-none-elf` | * | Bare RISC-V (RV64IMAC ISA)
168170
`sparc64-unknown-linux-gnu` | ✓ | SPARC Linux (kernel 4.4, glibc 2.23)
@@ -313,7 +315,6 @@ target | std | host | notes
313315
[`powerpc64-ibm-aix`](platform-support/aix.md) | ? | | 64-bit AIX (7.2 and newer)
314316
`riscv32gc-unknown-linux-gnu` | | | RISC-V Linux (kernel 5.4, glibc 2.33)
315317
`riscv32gc-unknown-linux-musl` | | | RISC-V Linux (kernel 5.4, musl + RISCV32 support patches)
316-
`riscv32im-unknown-none-elf` | * | | Bare RISC-V (RV32IM ISA)
317318
[`riscv32imac-unknown-xous-elf`](platform-support/riscv32imac-unknown-xous-elf.md) | ? | | RISC-V Xous (RV32IMAC ISA)
318319
[`riscv32imc-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF
319320
[`riscv32imac-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF

‎src/doc/rustc/src/platform-support/riscv32i-unknown-none-elf.md

+1
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
riscv32imac-unknown-none-elf.md

‎src/doc/rustc/src/platform-support/riscv32im-unknown-none-elf.md

+1
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
riscv32imac-unknown-none-elf.md

‎src/doc/rustc/src/platform-support/riscv32imac-unknown-none-elf.md

+34
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
# `riscv32{i,im,imc,imac,imafc}-unknown-none-elf`
2+
3+
**Tier: 2**
4+
5+
Bare-metal target for RISC-V CPUs with the RV32I, RV32IM, RV32IMC, RV32IMAFC and RV32IMAC ISAs.
6+
7+
## Target maintainers
8+
9+
* Rust Embedded Working Group, [RISC-V team](https://github.com/rust-embedded/wg#the-risc-v-team)
10+
11+
## Requirements
12+
13+
The target is cross-compiled, and uses static linking. No external toolchain
14+
is required and the default `rust-lld` linker works, but you must specify
15+
a linker script. The [`riscv-rt`] crate provides a suitable one. The
16+
[`riscv-rust-quickstart`] repository gives an example of an RV32 project.
17+
18+
[`riscv-rt`]: https://crates.io/crates/riscv-rt
19+
[`riscv-rust-quickstart`]: https://github.com/riscv-rust/riscv-rust-quickstart
20+
21+
## Building the target
22+
23+
This target is included in Rust and can be installed via `rustup`.
24+
25+
## Testing
26+
27+
This is a cross-compiled no-std target, which must be run either in a simulator
28+
or by programming them onto suitable hardware. It is not possible to run the
29+
Rust testsuite on this target.
30+
31+
## Cross-compilation toolchains and C code
32+
33+
This target supports C code. If interlinking with C or C++, you may need to use
34+
riscv64-unknown-elf-gcc as a linker instead of rust-lld.

‎src/doc/rustc/src/platform-support/riscv32imafc-unknown-none-elf.md

+1
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
riscv32imac-unknown-none-elf.md

‎src/doc/rustc/src/platform-support/riscv32imc-unknown-none-elf.md

+1
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
riscv32imac-unknown-none-elf.md

‎src/tools/build-manifest/src/main.rs

+1
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,7 @@ static TARGETS: &[&str] = &[
123123
"riscv32im-unknown-none-elf",
124124
"riscv32imc-unknown-none-elf",
125125
"riscv32imac-unknown-none-elf",
126+
"riscv32imafc-unknown-none-elf",
126127
"riscv32gc-unknown-linux-gnu",
127128
"riscv64imac-unknown-none-elf",
128129
"riscv64gc-unknown-hermit",

0 commit comments

Comments
 (0)