22
33use cranelift_codegen:: ir:: immediates:: Offset32 ;
44use rustc_abi:: Endian ;
5+ use rustc_middle:: ty:: SimdAlign ;
56
67use super :: * ;
78use crate :: prelude:: * ;
@@ -960,6 +961,15 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
960961 let lane_clif_ty = fx. clif_type ( val_lane_ty) . unwrap ( ) ;
961962 let ptr_val = ptr. load_scalar ( fx) ;
962963
964+ let alignment = generic_args[ 3 ] . expect_const ( ) . to_value ( ) . valtree . unwrap_branch ( ) [ 0 ]
965+ . unwrap_leaf ( )
966+ . to_simd_alignment ( ) ;
967+
968+ let memflags = match alignment {
969+ SimdAlign :: Unaligned => MemFlags :: new ( ) . with_notrap ( ) ,
970+ _ => MemFlags :: trusted ( ) ,
971+ } ;
972+
963973 for lane_idx in 0 ..val_lane_count {
964974 let val_lane = val. value_lane ( fx, lane_idx) . load_scalar ( fx) ;
965975 let mask_lane = mask. value_lane ( fx, lane_idx) . load_scalar ( fx) ;
@@ -972,7 +982,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
972982
973983 fx. bcx . switch_to_block ( if_enabled) ;
974984 let offset = lane_idx as i32 * lane_clif_ty. bytes ( ) as i32 ;
975- fx. bcx . ins ( ) . store ( MemFlags :: trusted ( ) , val_lane, ptr_val, Offset32 :: new ( offset) ) ;
985+ fx. bcx . ins ( ) . store ( memflags , val_lane, ptr_val, Offset32 :: new ( offset) ) ;
976986 fx. bcx . ins ( ) . jump ( next, & [ ] ) ;
977987
978988 fx. bcx . seal_block ( next) ;
@@ -996,6 +1006,15 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
9961006 let lane_clif_ty = fx. clif_type ( val_lane_ty) . unwrap ( ) ;
9971007 let ret_lane_layout = fx. layout_of ( ret_lane_ty) ;
9981008
1009+ let alignment = generic_args[ 3 ] . expect_const ( ) . to_value ( ) . valtree . unwrap_branch ( ) [ 0 ]
1010+ . unwrap_leaf ( )
1011+ . to_simd_alignment ( ) ;
1012+
1013+ let memflags = match alignment {
1014+ SimdAlign :: Unaligned => MemFlags :: new ( ) . with_notrap ( ) ,
1015+ _ => MemFlags :: trusted ( ) ,
1016+ } ;
1017+
9991018 for lane_idx in 0 ..ptr_lane_count {
10001019 let val_lane = val. value_lane ( fx, lane_idx) . load_scalar ( fx) ;
10011020 let ptr_lane = ptr. value_lane ( fx, lane_idx) . load_scalar ( fx) ;
@@ -1011,7 +1030,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
10111030 fx. bcx . seal_block ( if_disabled) ;
10121031
10131032 fx. bcx . switch_to_block ( if_enabled) ;
1014- let res = fx. bcx . ins ( ) . load ( lane_clif_ty, MemFlags :: trusted ( ) , ptr_lane, 0 ) ;
1033+ let res = fx. bcx . ins ( ) . load ( lane_clif_ty, memflags , ptr_lane, 0 ) ;
10151034 fx. bcx . ins ( ) . jump ( next, & [ res. into ( ) ] ) ;
10161035
10171036 fx. bcx . switch_to_block ( if_disabled) ;
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