Skip to content

Commit acf1ff8

Browse files
borsbors
committed
Auto merge of #134133 - fmease:rollup-6pmsnag, r=fmease
Rollup of 9 pull requests Successful merges: - #134042 (Add the `power8-crypto` target feature) - #134070 (Some asm! diagnostic adjustments and a papercut fix) - #134094 (Tweak wording of non-const traits used as const bounds) - #134100 (Remove rustc_const_stable attribute on const NOOP) - #134103 (Don't ICE when encountering never in range pattern) - #134113 (run-make: Fix `assert_stderr_not_contains_regex`) - #134115 (rustc_target: ppc64 target string fixes for LLVM 20) - #134116 (stabilize const_nonnull_new) - #134120 (Remove Felix from ping groups and review rotation) r? `@ghost` `@rustbot` modify labels: rollup
2 parents 33c245b + a36ceba commit acf1ff8

File tree

75 files changed

+1305
-257
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

75 files changed

+1305
-257
lines changed

‎compiler/rustc_codegen_llvm/src/context.rs

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -159,6 +159,11 @@ pub(crate) unsafe fn create_module<'ll>(
159159
// See https://github.com/llvm/llvm-project/pull/112084
160160
target_data_layout = target_data_layout.replace("-i128:128", "");
161161
}
162+
if sess.target.arch.starts_with("powerpc64") {
163+
// LLVM 20 updates the powerpc64 layout to correctly align 128 bit integers to 128 bit.
164+
// See https://github.com/llvm/llvm-project/pull/118004
165+
target_data_layout = target_data_layout.replace("-i128:128", "");
166+
}
162167
}
163168

164169
// Ensure the data-layout values hardcoded remain the defaults.

‎compiler/rustc_codegen_llvm/src/llvm_util.rs

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -230,6 +230,8 @@ pub(crate) fn to_llvm_features<'a>(sess: &Session, s: &'a str) -> Option<LLVMFea
230230
"aarch64"
231231
} else if sess.target.arch == "sparc64" {
232232
"sparc"
233+
} else if sess.target.arch == "powerpc64" {
234+
"powerpc"
233235
} else {
234236
&*sess.target.arch
235237
};
@@ -289,6 +291,7 @@ pub(crate) fn to_llvm_features<'a>(sess: &Session, s: &'a str) -> Option<LLVMFea
289291
// https://github.com/llvm/llvm-project/blob/llvmorg-18.1.0/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp#L26
290292
("sparc", "v8plus") if get_version().0 == 19 => Some(LLVMFeature::new("v9")),
291293
("sparc", "v8plus") if get_version().0 < 19 => None,
294+
("powerpc", "power8-crypto") => Some(LLVMFeature::new("crypto")),
292295
(_, s) => Some(LLVMFeature::new(s)),
293296
}
294297
}

‎compiler/rustc_hir_analysis/messages.ftl

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -96,12 +96,14 @@ hir_analysis_coercion_between_struct_same_note = expected coercion between the s
9696
9797
hir_analysis_coercion_between_struct_single_note = expected a single field to be coerced, none found
9898
99-
hir_analysis_const_bound_for_non_const_trait =
100-
`{$modifier}` can only be applied to `#[const_trait]` traits
101-
102-
hir_analysis_const_impl_for_non_const_trait =
103-
const `impl` for trait `{$trait_name}` which is not marked with `#[const_trait]`
104-
.suggestion = mark `{$trait_name}` as const
99+
hir_analysis_const_bound_for_non_const_trait = `{$modifier}` can only be applied to `#[const_trait]` traits
100+
.label = can't be applied to `{$trait_name}`
101+
.note = `{$trait_name}` can't be used with `{$modifier}` because it isn't annotated with `#[const_trait]`
102+
.suggestion = {$suggestion_pre}mark `{$trait_name}` as `#[const_trait]` to allow it to have `const` implementations
103+
104+
hir_analysis_const_impl_for_non_const_trait = const `impl` for trait `{$trait_name}` which is not marked with `#[const_trait]`
105+
.label = this trait is not `const`
106+
.suggestion = {$suggestion_pre}mark `{$trait_name}` as `#[const_trait]` to allow it to have `const` implementations
105107
.note = marking a trait with `#[const_trait]` ensures all default method bodies are `const`
106108
.adding = adding a non-const method body in the future would be a breaking change
107109

‎compiler/rustc_hir_analysis/src/check/intrinsicck.rs

Lines changed: 74 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@ use std::assert_matches::debug_assert_matches;
33
use rustc_abi::FieldIdx;
44
use rustc_ast::InlineAsmTemplatePiece;
55
use rustc_data_structures::fx::FxIndexSet;
6+
use rustc_hir::def_id::DefId;
67
use rustc_hir::{self as hir, LangItem};
78
use rustc_middle::bug;
89
use rustc_middle::ty::{self, FloatTy, IntTy, Ty, TyCtxt, TypeVisitableExt, UintTy};
@@ -21,6 +22,12 @@ pub struct InlineAsmCtxt<'a, 'tcx> {
2122
get_operand_ty: Box<dyn Fn(&'tcx hir::Expr<'tcx>) -> Ty<'tcx> + 'a>,
2223
}
2324

25+
enum NonAsmTypeReason<'tcx> {
26+
UnevaluatedSIMDArrayLength(DefId, ty::Const<'tcx>),
27+
Invalid(Ty<'tcx>),
28+
InvalidElement(DefId, Ty<'tcx>),
29+
}
30+
2431
impl<'a, 'tcx> InlineAsmCtxt<'a, 'tcx> {
2532
pub fn new_global_asm(tcx: TyCtxt<'tcx>) -> Self {
2633
InlineAsmCtxt {
@@ -56,7 +63,7 @@ impl<'a, 'tcx> InlineAsmCtxt<'a, 'tcx> {
5663
false
5764
}
5865

59-
fn get_asm_ty(&self, ty: Ty<'tcx>) -> Option<InlineAsmType> {
66+
fn get_asm_ty(&self, ty: Ty<'tcx>) -> Result<InlineAsmType, NonAsmTypeReason<'tcx>> {
6067
let asm_ty_isize = match self.tcx.sess.target.pointer_width {
6168
16 => InlineAsmType::I16,
6269
32 => InlineAsmType::I32,
@@ -65,64 +72,62 @@ impl<'a, 'tcx> InlineAsmCtxt<'a, 'tcx> {
6572
};
6673

6774
match *ty.kind() {
68-
ty::Int(IntTy::I8) | ty::Uint(UintTy::U8) => Some(InlineAsmType::I8),
69-
ty::Int(IntTy::I16) | ty::Uint(UintTy::U16) => Some(InlineAsmType::I16),
70-
ty::Int(IntTy::I32) | ty::Uint(UintTy::U32) => Some(InlineAsmType::I32),
71-
ty::Int(IntTy::I64) | ty::Uint(UintTy::U64) => Some(InlineAsmType::I64),
72-
ty::Int(IntTy::I128) | ty::Uint(UintTy::U128) => Some(InlineAsmType::I128),
73-
ty::Int(IntTy::Isize) | ty::Uint(UintTy::Usize) => Some(asm_ty_isize),
74-
ty::Float(FloatTy::F16) => Some(InlineAsmType::F16),
75-
ty::Float(FloatTy::F32) => Some(InlineAsmType::F32),
76-
ty::Float(FloatTy::F64) => Some(InlineAsmType::F64),
77-
ty::Float(FloatTy::F128) => Some(InlineAsmType::F128),
78-
ty::FnPtr(..) => Some(asm_ty_isize),
79-
ty::RawPtr(ty, _) if self.is_thin_ptr_ty(ty) => Some(asm_ty_isize),
75+
ty::Int(IntTy::I8) | ty::Uint(UintTy::U8) => Ok(InlineAsmType::I8),
76+
ty::Int(IntTy::I16) | ty::Uint(UintTy::U16) => Ok(InlineAsmType::I16),
77+
ty::Int(IntTy::I32) | ty::Uint(UintTy::U32) => Ok(InlineAsmType::I32),
78+
ty::Int(IntTy::I64) | ty::Uint(UintTy::U64) => Ok(InlineAsmType::I64),
79+
ty::Int(IntTy::I128) | ty::Uint(UintTy::U128) => Ok(InlineAsmType::I128),
80+
ty::Int(IntTy::Isize) | ty::Uint(UintTy::Usize) => Ok(asm_ty_isize),
81+
ty::Float(FloatTy::F16) => Ok(InlineAsmType::F16),
82+
ty::Float(FloatTy::F32) => Ok(InlineAsmType::F32),
83+
ty::Float(FloatTy::F64) => Ok(InlineAsmType::F64),
84+
ty::Float(FloatTy::F128) => Ok(InlineAsmType::F128),
85+
ty::FnPtr(..) => Ok(asm_ty_isize),
86+
ty::RawPtr(ty, _) if self.is_thin_ptr_ty(ty) => Ok(asm_ty_isize),
8087
ty::Adt(adt, args) if adt.repr().simd() => {
8188
let fields = &adt.non_enum_variant().fields;
82-
let elem_ty = fields[FieldIdx::ZERO].ty(self.tcx, args);
89+
let field = &fields[FieldIdx::ZERO];
90+
let elem_ty = field.ty(self.tcx, args);
8391

8492
let (size, ty) = match elem_ty.kind() {
8593
ty::Array(ty, len) => {
94+
let len = self.tcx.normalize_erasing_regions(self.typing_env, *len);
8695
if let Some(len) = len.try_to_target_usize(self.tcx) {
8796
(len, *ty)
8897
} else {
89-
return None;
98+
return Err(NonAsmTypeReason::UnevaluatedSIMDArrayLength(
99+
field.did, len,
100+
));
90101
}
91102
}
92103
_ => (fields.len() as u64, elem_ty),
93104
};
94105

95106
match ty.kind() {
96-
ty::Int(IntTy::I8) | ty::Uint(UintTy::U8) => Some(InlineAsmType::VecI8(size)),
97-
ty::Int(IntTy::I16) | ty::Uint(UintTy::U16) => {
98-
Some(InlineAsmType::VecI16(size))
99-
}
100-
ty::Int(IntTy::I32) | ty::Uint(UintTy::U32) => {
101-
Some(InlineAsmType::VecI32(size))
102-
}
103-
ty::Int(IntTy::I64) | ty::Uint(UintTy::U64) => {
104-
Some(InlineAsmType::VecI64(size))
105-
}
107+
ty::Int(IntTy::I8) | ty::Uint(UintTy::U8) => Ok(InlineAsmType::VecI8(size)),
108+
ty::Int(IntTy::I16) | ty::Uint(UintTy::U16) => Ok(InlineAsmType::VecI16(size)),
109+
ty::Int(IntTy::I32) | ty::Uint(UintTy::U32) => Ok(InlineAsmType::VecI32(size)),
110+
ty::Int(IntTy::I64) | ty::Uint(UintTy::U64) => Ok(InlineAsmType::VecI64(size)),
106111
ty::Int(IntTy::I128) | ty::Uint(UintTy::U128) => {
107-
Some(InlineAsmType::VecI128(size))
112+
Ok(InlineAsmType::VecI128(size))
108113
}
109114
ty::Int(IntTy::Isize) | ty::Uint(UintTy::Usize) => {
110-
Some(match self.tcx.sess.target.pointer_width {
115+
Ok(match self.tcx.sess.target.pointer_width {
111116
16 => InlineAsmType::VecI16(size),
112117
32 => InlineAsmType::VecI32(size),
113118
64 => InlineAsmType::VecI64(size),
114119
width => bug!("unsupported pointer width: {width}"),
115120
})
116121
}
117-
ty::Float(FloatTy::F16) => Some(InlineAsmType::VecF16(size)),
118-
ty::Float(FloatTy::F32) => Some(InlineAsmType::VecF32(size)),
119-
ty::Float(FloatTy::F64) => Some(InlineAsmType::VecF64(size)),
120-
ty::Float(FloatTy::F128) => Some(InlineAsmType::VecF128(size)),
121-
_ => None,
122+
ty::Float(FloatTy::F16) => Ok(InlineAsmType::VecF16(size)),
123+
ty::Float(FloatTy::F32) => Ok(InlineAsmType::VecF32(size)),
124+
ty::Float(FloatTy::F64) => Ok(InlineAsmType::VecF64(size)),
125+
ty::Float(FloatTy::F128) => Ok(InlineAsmType::VecF128(size)),
126+
_ => Err(NonAsmTypeReason::InvalidElement(field.did, ty)),
122127
}
123128
}
124129
ty::Infer(_) => bug!("unexpected infer ty in asm operand"),
125-
_ => None,
130+
_ => Err(NonAsmTypeReason::Invalid(ty)),
126131
}
127132
}
128133

@@ -163,17 +168,42 @@ impl<'a, 'tcx> InlineAsmCtxt<'a, 'tcx> {
163168
}
164169
_ => self.get_asm_ty(ty),
165170
};
166-
let Some(asm_ty) = asm_ty else {
167-
let msg = format!("cannot use value of type `{ty}` for inline assembly");
168-
self.tcx
169-
.dcx()
170-
.struct_span_err(expr.span, msg)
171-
.with_note(
172-
"only integers, floats, SIMD vectors, pointers and function pointers \
173-
can be used as arguments for inline assembly",
174-
)
175-
.emit();
176-
return None;
171+
let asm_ty = match asm_ty {
172+
Ok(asm_ty) => asm_ty,
173+
Err(reason) => {
174+
match reason {
175+
NonAsmTypeReason::UnevaluatedSIMDArrayLength(did, len) => {
176+
let msg = format!("cannot evaluate SIMD vector length `{len}`");
177+
self.tcx
178+
.dcx()
179+
.struct_span_err(self.tcx.def_span(did), msg)
180+
.with_span_note(
181+
expr.span,
182+
"SIMD vector length needs to be known statically for use in `asm!`",
183+
)
184+
.emit();
185+
}
186+
NonAsmTypeReason::Invalid(ty) => {
187+
let msg = format!("cannot use value of type `{ty}` for inline assembly");
188+
self.tcx.dcx().struct_span_err(expr.span, msg).with_note(
189+
"only integers, floats, SIMD vectors, pointers and function pointers \
190+
can be used as arguments for inline assembly",
191+
).emit();
192+
}
193+
NonAsmTypeReason::InvalidElement(did, ty) => {
194+
let msg = format!(
195+
"cannot use SIMD vector with element type `{ty}` for inline assembly"
196+
);
197+
self.tcx.dcx()
198+
.struct_span_err(self.tcx.def_span(did), msg).with_span_note(
199+
expr.span,
200+
"only integers, floats, SIMD vectors, pointers and function pointers \
201+
can be used as arguments for inline assembly",
202+
).emit();
203+
}
204+
}
205+
return None;
206+
}
177207
};
178208

179209
// Check that the type implements Copy. The only case where this can

‎compiler/rustc_hir_analysis/src/collect.rs

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1638,11 +1638,23 @@ fn check_impl_constness(
16381638
}
16391639

16401640
let trait_name = tcx.item_name(trait_def_id).to_string();
1641+
let (local_trait_span, suggestion_pre) =
1642+
match (trait_def_id.is_local(), tcx.sess.is_nightly_build()) {
1643+
(true, true) => (
1644+
Some(tcx.def_span(trait_def_id).shrink_to_lo()),
1645+
if tcx.features().const_trait_impl() {
1646+
""
1647+
} else {
1648+
"enable `#![feature(const_trait_impl)]` in your crate and "
1649+
},
1650+
),
1651+
(false, _) | (_, false) => (None, ""),
1652+
};
16411653
Some(tcx.dcx().emit_err(errors::ConstImplForNonConstTrait {
16421654
trait_ref_span: hir_trait_ref.path.span,
16431655
trait_name,
1644-
local_trait_span:
1645-
trait_def_id.as_local().map(|_| tcx.def_span(trait_def_id).shrink_to_lo()),
1656+
local_trait_span,
1657+
suggestion_pre,
16461658
marking: (),
16471659
adding: (),
16481660
}))

‎compiler/rustc_hir_analysis/src/errors.rs

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -530,10 +530,16 @@ pub(crate) struct GenericArgsOnOverriddenImpl {
530530
#[diag(hir_analysis_const_impl_for_non_const_trait)]
531531
pub(crate) struct ConstImplForNonConstTrait {
532532
#[primary_span]
533+
#[label]
533534
pub trait_ref_span: Span,
534535
pub trait_name: String,
535-
#[suggestion(applicability = "machine-applicable", code = "#[const_trait]")]
536+
#[suggestion(
537+
applicability = "machine-applicable",
538+
code = "#[const_trait] ",
539+
style = "verbose"
540+
)]
536541
pub local_trait_span: Option<Span>,
542+
pub suggestion_pre: &'static str,
537543
#[note]
538544
pub marking: (),
539545
#[note(hir_analysis_adding)]
@@ -544,8 +550,19 @@ pub(crate) struct ConstImplForNonConstTrait {
544550
#[diag(hir_analysis_const_bound_for_non_const_trait)]
545551
pub(crate) struct ConstBoundForNonConstTrait {
546552
#[primary_span]
553+
#[label]
547554
pub span: Span,
548555
pub modifier: &'static str,
556+
#[note]
557+
pub def_span: Option<Span>,
558+
pub suggestion_pre: &'static str,
559+
#[suggestion(
560+
applicability = "machine-applicable",
561+
code = "#[const_trait] ",
562+
style = "verbose"
563+
)]
564+
pub suggestion: Option<Span>,
565+
pub trait_name: String,
549566
}
550567

551568
#[derive(Diagnostic)]

‎compiler/rustc_hir_analysis/src/hir_ty_lowering/mod.rs

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -737,9 +737,26 @@ impl<'tcx> dyn HirTyLowerer<'tcx> + '_ {
737737
if let hir::BoundConstness::Always(span) | hir::BoundConstness::Maybe(span) = constness
738738
&& !self.tcx().is_const_trait(trait_def_id)
739739
{
740+
let (def_span, suggestion, suggestion_pre) =
741+
match (trait_def_id.is_local(), self.tcx().sess.is_nightly_build()) {
742+
(true, true) => (
743+
None,
744+
Some(tcx.def_span(trait_def_id).shrink_to_lo()),
745+
if self.tcx().features().const_trait_impl() {
746+
""
747+
} else {
748+
"enable `#![feature(const_trait_impl)]` in your crate and "
749+
},
750+
),
751+
(false, _) | (_, false) => (Some(tcx.def_span(trait_def_id)), None, ""),
752+
};
740753
self.dcx().emit_err(crate::errors::ConstBoundForNonConstTrait {
741754
span,
742755
modifier: constness.as_str(),
756+
def_span,
757+
trait_name: self.tcx().def_path_str(trait_def_id),
758+
suggestion_pre,
759+
suggestion,
743760
});
744761
}
745762

‎compiler/rustc_hir_typeck/src/expr.rs

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -403,6 +403,11 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> {
403403
})
404404
| hir::Node::ImplItem(hir::ImplItem { kind: hir::ImplItemKind::Const(..), .. }) => true,
405405

406+
hir::Node::Pat(_) => {
407+
self.dcx().span_delayed_bug(expr.span, "place expr not allowed in pattern");
408+
true
409+
}
410+
406411
// These nodes do not have direct sub-exprs.
407412
hir::Node::Param(_)
408413
| hir::Node::Item(_)
@@ -415,7 +420,6 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> {
415420
| hir::Node::Ty(_)
416421
| hir::Node::AssocItemConstraint(_)
417422
| hir::Node::TraitRef(_)
418-
| hir::Node::Pat(_)
419423
| hir::Node::PatField(_)
420424
| hir::Node::LetStmt(_)
421425
| hir::Node::Synthetic

‎compiler/rustc_target/src/spec/targets/powerpc64_ibm_aix.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ pub(crate) fn target() -> Target {
1919
std: None, // ?
2020
},
2121
pointer_width: 64,
22-
data_layout: "E-m:a-Fi64-i64:64-n32:64-S128-v256:256:256-v512:512:512".into(),
22+
data_layout: "E-m:a-Fi64-i64:64-i128:128-n32:64-S128-v256:256:256-v512:512:512".into(),
2323
arch: "powerpc64".into(),
2424
options: base,
2525
}

‎compiler/rustc_target/src/spec/targets/powerpc64_unknown_freebsd.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ pub(crate) fn target() -> Target {
1717
std: Some(true),
1818
},
1919
pointer_width: 64,
20-
data_layout: "E-m:e-Fn32-i64:64-n32:64".into(),
20+
data_layout: "E-m:e-Fn32-i64:64-i128:128-n32:64".into(),
2121
arch: "powerpc64".into(),
2222
options: TargetOptions { endian: Endian::Big, mcount: "_mcount".into(), ..base },
2323
}

‎compiler/rustc_target/src/spec/targets/powerpc64_unknown_linux_gnu.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ pub(crate) fn target() -> Target {
1717
std: Some(true),
1818
},
1919
pointer_width: 64,
20-
data_layout: "E-m:e-Fi64-i64:64-n32:64-S128-v256:256:256-v512:512:512".into(),
20+
data_layout: "E-m:e-Fi64-i64:64-i128:128-n32:64-S128-v256:256:256-v512:512:512".into(),
2121
arch: "powerpc64".into(),
2222
options: TargetOptions { endian: Endian::Big, mcount: "_mcount".into(), ..base },
2323
}

‎compiler/rustc_target/src/spec/targets/powerpc64_unknown_linux_musl.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ pub(crate) fn target() -> Target {
1717
std: Some(true),
1818
},
1919
pointer_width: 64,
20-
data_layout: "E-m:e-Fn32-i64:64-n32:64-S128-v256:256:256-v512:512:512".into(),
20+
data_layout: "E-m:e-Fn32-i64:64-i128:128-n32:64-S128-v256:256:256-v512:512:512".into(),
2121
arch: "powerpc64".into(),
2222
options: TargetOptions { endian: Endian::Big, mcount: "_mcount".into(), ..base },
2323
}

‎compiler/rustc_target/src/spec/targets/powerpc64_unknown_openbsd.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ pub(crate) fn target() -> Target {
1717
std: Some(true),
1818
},
1919
pointer_width: 64,
20-
data_layout: "E-m:e-Fn32-i64:64-n32:64".into(),
20+
data_layout: "E-m:e-Fn32-i64:64-i128:128-n32:64".into(),
2121
arch: "powerpc64".into(),
2222
options: TargetOptions { endian: Endian::Big, mcount: "_mcount".into(), ..base },
2323
}

‎compiler/rustc_target/src/spec/targets/powerpc64_wrs_vxworks.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ pub(crate) fn target() -> Target {
1717
std: Some(true),
1818
},
1919
pointer_width: 64,
20-
data_layout: "E-m:e-Fi64-i64:64-n32:64-S128-v256:256:256-v512:512:512".into(),
20+
data_layout: "E-m:e-Fi64-i64:64-i128:128-n32:64-S128-v256:256:256-v512:512:512".into(),
2121
arch: "powerpc64".into(),
2222
options: TargetOptions { endian: Endian::Big, ..base },
2323
}

0 commit comments

Comments
 (0)