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ManishearthManishearth
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Rollup merge of #73214 - androm3da:hex_inline_asm_00, r=Amanieu
Add asm!() support for hexagon
2 parents 55479de + 7a9f29d commit bc773fe

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‎src/doc/unstable-book/src/library-features/asm.md

+10-3
Original file line numberDiff line numberDiff line change
@@ -374,7 +374,7 @@ options := "options(" option *["," option] [","] ")"
374374
asm := "asm!(" format_string *("," [ident "="] operand) ["," options] [","] ")"
375375
```
376376

377-
The macro will initially be supported only on ARM, AArch64, x86, x86-64 and RISC-V targets. Support for more targets may be added in the future. The compiler will emit an error if `asm!` is used on an unsupported target.
377+
The macro will initially be supported only on ARM, AArch64, Hexagon, x86, x86-64 and RISC-V targets. Support for more targets may be added in the future. The compiler will emit an error if `asm!` is used on an unsupported target.
378378

379379
[format-syntax]: https://doc.rust-lang.org/std/fmt/#syntax
380380

@@ -388,7 +388,7 @@ Explicit register operands cannot be used by placeholders in the template string
388388

389389
The exact assembly code syntax is target-specific and opaque to the compiler except for the way operands are substituted into the template string to form the code passed to the assembler.
390390

391-
The 4 targets specified in this RFC (x86, ARM, AArch64, RISC-V) all use the assembly code syntax of the GNU assembler (GAS). On x86, the `.intel_syntax noprefix` mode of GAS is used by default. On ARM, the `.syntax unified` mode is used. These targets impose an additional restriction on the assembly code: any assembler state (e.g. the current section which can be changed with `.section`) must be restored to its original value at the end of the asm string. Assembly code that does not conform to the GAS syntax will result in assembler-specific behavior.
391+
The 5 targets specified in this RFC (x86, ARM, AArch64, RISC-V, Hexagon) all use the assembly code syntax of the GNU assembler (GAS). On x86, the `.intel_syntax noprefix` mode of GAS is used by default. On ARM, the `.syntax unified` mode is used. These targets impose an additional restriction on the assembly code: any assembler state (e.g. the current section which can be changed with `.section`) must be restored to its original value at the end of the asm string. Assembly code that does not conform to the GAS syntax will result in assembler-specific behavior.
392392

393393
[rfc-2795]: https://github.com/rust-lang/rfcs/pull/2795
394394

@@ -475,6 +475,7 @@ Here is the list of currently supported register classes:
475475
| NVPTX | `reg64` | None\* | `l` |
476476
| RISC-V | `reg` | `x1`, `x[5-7]`, `x[9-15]`, `x[16-31]` (non-RV32E) | `r` |
477477
| RISC-V | `freg` | `f[0-31]` | `f` |
478+
| Hexagon | `reg` | `r[0-28]` | `r` |
478479

479480
> **Note**: On x86 we treat `reg_byte` differently from `reg` because the compiler can allocate `al` and `ah` separately whereas `reg` reserves the whole register.
480481
>
@@ -509,6 +510,7 @@ Each register class has constraints on which value types they can be used with.
509510
| RISC-V64 | `reg` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
510511
| RISC-V | `freg` | `f` | `f32` |
511512
| RISC-V | `freg` | `d` | `f64` |
513+
| Hexagon | `reg` | None | `i8`, `i16`, `i32`, `f32` |
512514

513515
> **Note**: For the purposes of the above table pointers, function pointers and `isize`/`usize` are treated as the equivalent integer type (`i16`/`i32`/`i64` depending on the target).
514516
@@ -565,13 +567,16 @@ Some registers have multiple names. These are all treated by the compiler as ide
565567
| RISC-V | `f[10-17]` | `fa[0-7]` |
566568
| RISC-V | `f[18-27]` | `fs[2-11]` |
567569
| RISC-V | `f[28-31]` | `ft[8-11]` |
570+
| Hexagon | `r29` | `sp` |
571+
| Hexagon | `r30` | `fr` |
572+
| Hexagon | `r31` | `lr` |
568573

569574
Some registers cannot be used for input or output operands:
570575

571576
| Architecture | Unsupported register | Reason |
572577
| ------------ | -------------------- | ------ |
573578
| All | `sp` | The stack pointer must be restored to its original value at the end of an asm code block. |
574-
| All | `bp` (x86), `r11` (ARM), `x29` (AArch64), `x8` (RISC-V) | The frame pointer cannot be used as an input or output. |
579+
| All | `bp` (x86), `r11` (ARM), `x29` (AArch64), `x8` (RISC-V), `fr` (Hexagon) | The frame pointer cannot be used as an input or output. |
575580
| x86 | `k0` | This is a constant zero register which can't be modified. |
576581
| x86 | `ip` | This is the program counter, not a real register. |
577582
| x86 | `mm[0-7]` | MMX registers are not currently supported (but may be in the future). |
@@ -580,6 +585,7 @@ Some registers cannot be used for input or output operands:
580585
| ARM | `pc` | This is the program counter, not a real register. |
581586
| RISC-V | `x0` | This is a constant zero register which can't be modified. |
582587
| RISC-V | `gp`, `tp` | These registers are reserved and cannot be used as inputs or outputs. |
588+
| Hexagon | `lr` | This is the link register which cannot be used as an input or output. |
583589

584590
## Template modifiers
585591

@@ -625,6 +631,7 @@ The supported modifiers are a subset of LLVM's (and GCC's) [asm template argumen
625631
| NVPTX | `reg64` | None | `rd0` | None |
626632
| RISC-V | `reg` | None | `x1` | None |
627633
| RISC-V | `freg` | None | `f0` | None |
634+
| Hexagon | `reg` | None | `r0` | None |
628635

629636
> Notes:
630637
> - on ARM `e` / `f`: this prints the low or high doubleword register name of a NEON quad (128-bit) register.

‎src/librustc_codegen_llvm/asm.rs

+4
Original file line numberDiff line numberDiff line change
@@ -255,6 +255,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
255255
}
256256
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
257257
InlineAsmArch::Nvptx64 => {}
258+
InlineAsmArch::Hexagon => {}
258259
}
259260
}
260261
if !options.contains(InlineAsmOptions::NOMEM) {
@@ -427,6 +428,7 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass) -> String {
427428
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => "x",
428429
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
429430
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
431+
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
430432
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
431433
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
432434
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
@@ -472,6 +474,7 @@ fn modifier_to_llvm(
472474
modifier
473475
}
474476
}
477+
InlineAsmRegClass::Hexagon(_) => None,
475478
InlineAsmRegClass::Nvptx(_) => None,
476479
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
477480
| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
@@ -523,6 +526,7 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
523526
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
524527
cx.type_vector(cx.type_i64(), 2)
525528
}
529+
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
526530
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
527531
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
528532
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),

‎src/librustc_target/asm/hexagon.rs

+93
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,93 @@
1+
use super::{InlineAsmArch, InlineAsmType};
2+
use rustc_macros::HashStable_Generic;
3+
use std::fmt;
4+
5+
def_reg_class! {
6+
Hexagon HexagonInlineAsmRegClass {
7+
reg,
8+
}
9+
}
10+
11+
impl HexagonInlineAsmRegClass {
12+
pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
13+
&[]
14+
}
15+
16+
pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
17+
None
18+
}
19+
20+
pub fn suggest_modifier(
21+
self,
22+
_arch: InlineAsmArch,
23+
_ty: InlineAsmType,
24+
) -> Option<(char, &'static str)> {
25+
None
26+
}
27+
28+
pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
29+
None
30+
}
31+
32+
pub fn supported_types(
33+
self,
34+
_arch: InlineAsmArch,
35+
) -> &'static [(InlineAsmType, Option<&'static str>)] {
36+
match self {
37+
Self::reg => types! { _: I8, I16, I32, F32; },
38+
}
39+
}
40+
}
41+
42+
def_regs! {
43+
Hexagon HexagonInlineAsmReg HexagonInlineAsmRegClass {
44+
r0: reg = ["r0"],
45+
r1: reg = ["r1"],
46+
r2: reg = ["r2"],
47+
r3: reg = ["r3"],
48+
r4: reg = ["r4"],
49+
r5: reg = ["r5"],
50+
r6: reg = ["r6"],
51+
r7: reg = ["r7"],
52+
r8: reg = ["r8"],
53+
r9: reg = ["r9"],
54+
r10: reg = ["r10"],
55+
r11: reg = ["r11"],
56+
r12: reg = ["r12"],
57+
r13: reg = ["r13"],
58+
r14: reg = ["r14"],
59+
r15: reg = ["r15"],
60+
r16: reg = ["r16"],
61+
r17: reg = ["r17"],
62+
r18: reg = ["r18"],
63+
r19: reg = ["r19"],
64+
r20: reg = ["r20"],
65+
r21: reg = ["r21"],
66+
r22: reg = ["r22"],
67+
r23: reg = ["r23"],
68+
r24: reg = ["r24"],
69+
r25: reg = ["r25"],
70+
r26: reg = ["r26"],
71+
r27: reg = ["r27"],
72+
r28: reg = ["r28"],
73+
#error = ["r29", "sp"] =>
74+
"the stack pointer cannot be used as an operand for inline asm",
75+
#error = ["r30", "fr"] =>
76+
"the frame register cannot be used as an operand for inline asm",
77+
#error = ["r31", "lr"] =>
78+
"the link register cannot be used as an operand for inline asm",
79+
}
80+
}
81+
82+
impl HexagonInlineAsmReg {
83+
pub fn emit(
84+
self,
85+
out: &mut dyn fmt::Write,
86+
_arch: InlineAsmArch,
87+
_modifier: Option<char>,
88+
) -> fmt::Result {
89+
out.write_str(self.name())
90+
}
91+
92+
pub fn overlapping_regs(self, mut _cb: impl FnMut(HexagonInlineAsmReg)) {}
93+
}

‎src/librustc_target/asm/mod.rs

+27
Original file line numberDiff line numberDiff line change
@@ -148,12 +148,14 @@ macro_rules! types {
148148

149149
mod aarch64;
150150
mod arm;
151+
mod hexagon;
151152
mod nvptx;
152153
mod riscv;
153154
mod x86;
154155

155156
pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
156157
pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
158+
pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
157159
pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
158160
pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
159161
pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
@@ -167,6 +169,7 @@ pub enum InlineAsmArch {
167169
RiscV32,
168170
RiscV64,
169171
Nvptx64,
172+
Hexagon,
170173
}
171174

172175
impl FromStr for InlineAsmArch {
@@ -181,6 +184,7 @@ impl FromStr for InlineAsmArch {
181184
"riscv32" => Ok(Self::RiscV32),
182185
"riscv64" => Ok(Self::RiscV64),
183186
"nvptx64" => Ok(Self::Nvptx64),
187+
"hexagon" => Ok(Self::Hexagon),
184188
_ => Err(()),
185189
}
186190
}
@@ -203,6 +207,7 @@ pub enum InlineAsmReg {
203207
AArch64(AArch64InlineAsmReg),
204208
RiscV(RiscVInlineAsmReg),
205209
Nvptx(NvptxInlineAsmReg),
210+
Hexagon(HexagonInlineAsmReg),
206211
}
207212

208213
impl InlineAsmReg {
@@ -212,6 +217,7 @@ impl InlineAsmReg {
212217
Self::Arm(r) => r.name(),
213218
Self::AArch64(r) => r.name(),
214219
Self::RiscV(r) => r.name(),
220+
Self::Hexagon(r) => r.name(),
215221
}
216222
}
217223

@@ -221,6 +227,7 @@ impl InlineAsmReg {
221227
Self::Arm(r) => InlineAsmRegClass::Arm(r.reg_class()),
222228
Self::AArch64(r) => InlineAsmRegClass::AArch64(r.reg_class()),
223229
Self::RiscV(r) => InlineAsmRegClass::RiscV(r.reg_class()),
230+
Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
224231
}
225232
}
226233

@@ -246,6 +253,9 @@ impl InlineAsmReg {
246253
InlineAsmArch::Nvptx64 => {
247254
Self::Nvptx(NvptxInlineAsmReg::parse(arch, has_feature, &name)?)
248255
}
256+
InlineAsmArch::Hexagon => {
257+
Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, &name)?)
258+
}
249259
})
250260
}
251261

@@ -262,6 +272,7 @@ impl InlineAsmReg {
262272
Self::Arm(r) => r.emit(out, arch, modifier),
263273
Self::AArch64(r) => r.emit(out, arch, modifier),
264274
Self::RiscV(r) => r.emit(out, arch, modifier),
275+
Self::Hexagon(r) => r.emit(out, arch, modifier),
265276
}
266277
}
267278

@@ -271,6 +282,7 @@ impl InlineAsmReg {
271282
Self::Arm(r) => r.overlapping_regs(|r| cb(Self::Arm(r))),
272283
Self::AArch64(_) => cb(self),
273284
Self::RiscV(_) => cb(self),
285+
Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
274286
}
275287
}
276288
}
@@ -292,6 +304,7 @@ pub enum InlineAsmRegClass {
292304
AArch64(AArch64InlineAsmRegClass),
293305
RiscV(RiscVInlineAsmRegClass),
294306
Nvptx(NvptxInlineAsmRegClass),
307+
Hexagon(HexagonInlineAsmRegClass),
295308
}
296309

297310
impl InlineAsmRegClass {
@@ -302,6 +315,7 @@ impl InlineAsmRegClass {
302315
Self::AArch64(r) => r.name(),
303316
Self::RiscV(r) => r.name(),
304317
Self::Nvptx(r) => r.name(),
318+
Self::Hexagon(r) => r.name(),
305319
}
306320
}
307321

@@ -315,6 +329,7 @@ impl InlineAsmRegClass {
315329
Self::AArch64(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::AArch64),
316330
Self::RiscV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::RiscV),
317331
Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
332+
Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),
318333
}
319334
}
320335

@@ -335,6 +350,7 @@ impl InlineAsmRegClass {
335350
Self::AArch64(r) => r.suggest_modifier(arch, ty),
336351
Self::RiscV(r) => r.suggest_modifier(arch, ty),
337352
Self::Nvptx(r) => r.suggest_modifier(arch, ty),
353+
Self::Hexagon(r) => r.suggest_modifier(arch, ty),
338354
}
339355
}
340356

@@ -351,6 +367,7 @@ impl InlineAsmRegClass {
351367
Self::AArch64(r) => r.default_modifier(arch),
352368
Self::RiscV(r) => r.default_modifier(arch),
353369
Self::Nvptx(r) => r.default_modifier(arch),
370+
Self::Hexagon(r) => r.default_modifier(arch),
354371
}
355372
}
356373

@@ -366,6 +383,7 @@ impl InlineAsmRegClass {
366383
Self::AArch64(r) => r.supported_types(arch),
367384
Self::RiscV(r) => r.supported_types(arch),
368385
Self::Nvptx(r) => r.supported_types(arch),
386+
Self::Hexagon(r) => r.supported_types(arch),
369387
}
370388
}
371389

@@ -384,6 +402,9 @@ impl InlineAsmRegClass {
384402
Self::RiscV(RiscVInlineAsmRegClass::parse(arch, name)?)
385403
}
386404
InlineAsmArch::Nvptx64 => Self::Nvptx(NvptxInlineAsmRegClass::parse(arch, name)?),
405+
InlineAsmArch::Hexagon => {
406+
Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?)
407+
}
387408
})
388409
})
389410
}
@@ -397,6 +418,7 @@ impl InlineAsmRegClass {
397418
Self::AArch64(r) => r.valid_modifiers(arch),
398419
Self::RiscV(r) => r.valid_modifiers(arch),
399420
Self::Nvptx(r) => r.valid_modifiers(arch),
421+
Self::Hexagon(r) => r.valid_modifiers(arch),
400422
}
401423
}
402424
}
@@ -541,5 +563,10 @@ pub fn allocatable_registers(
541563
nvptx::fill_reg_map(arch, has_feature, &mut map);
542564
map
543565
}
566+
InlineAsmArch::Hexagon => {
567+
let mut map = hexagon::regclass_map();
568+
hexagon::fill_reg_map(arch, has_feature, &mut map);
569+
map
570+
}
544571
}
545572
}

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