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1 parent 69adc88 commit dc7c3cdCopy full SHA for dc7c3cd
src/libcore/num/mod.rs
@@ -644,7 +644,7 @@ macro_rules! int_impl {
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self.overflowing_shl(rhs).0
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}
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- /// Panic-free bitwise shift-left; yields `self >> mask(rhs)`,
+ /// Panic-free bitwise shift-right; yields `self >> mask(rhs)`,
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/// where `mask` removes any high-order bits of `rhs` that
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/// would cause the shift to exceed the bitwidth of the type.
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///
@@ -1446,7 +1446,7 @@ macro_rules! uint_impl {
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