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docs: Update platform support
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‎src/doc/rustc/src/SUMMARY.md

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- [x86_64-fortanix-unknown-sgx](platform-support/x86_64-fortanix-unknown-sgx.md)
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- [x86_64-unknown-linux-none.md](platform-support/x86_64-unknown-linux-none.md)
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- [x86_64-unknown-none](platform-support/x86_64-unknown-none.md)
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- [xtensa-*-none-elf](platform-support/xtensa.md)
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- [Targets](targets/index.md)
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- [Built-in Targets](targets/built-in.md)
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- [Custom Targets](targets/custom.md)

‎src/doc/rustc/src/platform-support.md

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`x86_64-wrs-vxworks` | ? | |
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[`x86_64h-apple-darwin`](platform-support/x86_64h-apple-darwin.md) | ✓ | ✓ | macOS with late-gen Intel (at least Haswell)
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[`x86_64-unknown-linux-none`](platform-support/x86_64-unknown-linux-none.md) | * | | 64-bit Linux with no libc
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`xtensa-esp32-none-elf` | | | Xtensa ESP32
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`xtensa-esp32-espidf` | | | Xtensa ESP32
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`xtensa-esp32s2-none-elf` | | | Xtensa ESP32-S2
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`xtensa-esp32s2-espidf` | | | Xtensa ESP32-S2
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`xtensa-esp32s3-none-elf` | | | Xtensa ESP32-S3
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`xtensa-esp32s3-espidf` | | | Xtensa ESP32-S3
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[`xtensa-esp32-none-elf`](platform-support/xtensa.md) | * | | Xtensa ESP32
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[`xtensa-esp32-espidf`](platform-support/esp-idf.md) | ✓ | | Xtensa ESP32
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[`xtensa-esp32s2-none-elf`](platform-support/xtensa.md) | * | | Xtensa ESP32-S2
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[`xtensa-esp32s2-espidf`](platform-support/esp-idf.md) | ✓ | | Xtensa ESP32-S2
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[`xtensa-esp32s3-none-elf`](platform-support/xtensa.md) | * | | Xtensa ESP32-S3
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[`xtensa-esp32s3-espidf`](platform-support/esp-idf.md) | ✓ | | Xtensa ESP32-S3
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[runs on NVIDIA GPUs]: https://github.com/japaric-archived/nvptx#targets

‎src/doc/rustc/src/platform-support/esp-idf.md

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- Ivan Markov [@ivmarkov](https://github.com/ivmarkov)
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- Scott Mabin [@MabezDev](https://github.com/MabezDev)
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- Sergio Gasquez [@SergioGasquez](https://github.com/SergioGasquez)
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## Requirements
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The target names follow this format: `$ARCH-esp-espidf`, where `$ARCH` specifies the target processor architecture. The following targets are currently defined:
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| Target name | Target CPU(s) | Minimum ESP-IDF version |
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| ------------------------ | --------------------------------------------------------------- | ----------------------- |
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| `riscv32imc-esp-espidf` | [ESP32-C2](https://www.espressif.com/en/products/socs/esp32-c2) | `v5.0` |
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| `riscv32imc-esp-espidf` | [ESP32-C3](https://www.espressif.com/en/products/socs/esp32-c3) | `v4.3` |
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| `riscv32imac-esp-espidf` | [ESP32-C6](https://www.espressif.com/en/products/socs/esp32-c6) | `v5.1` |
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| `riscv32imac-esp-espidf` | [ESP32-H2](https://www.espressif.com/en/products/socs/esp32-h2) | `v5.1` |
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| `riscv32imafc-esp-espidf`| [ESP32-P4](https://www.espressif.com/en/news/ESP32-P4) | `v5.2` |
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| Target name | Target CPU(s) | Minimum ESP-IDF version |
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| ------------------------- | --------------------------------------------------------------- | ----------------------- |
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| `riscv32imc-esp-espidf` | [ESP32-C2](https://www.espressif.com/en/products/socs/esp32-c2) | `v5.0` |
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| `riscv32imc-esp-espidf` | [ESP32-C3](https://www.espressif.com/en/products/socs/esp32-c3) | `v4.4` |
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| `riscv32imac-esp-espidf` | [ESP32-C6](https://www.espressif.com/en/products/socs/esp32-c6) | `v5.1` |
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| `riscv32imac-esp-espidf` | [ESP32-H2](https://www.espressif.com/en/products/socs/esp32-h2) | `v5.1` |
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| `riscv32imafc-esp-espidf` | [ESP32-P4](https://www.espressif.com/en/news/ESP32-P4) | `v5.2` |
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| `xtensa-esp32-espidf` | [ESP32](https://www.espressif.com/en/products/socs/esp32) | `v4.4` |
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| `xtensa-esp32s2-espidf` | [ESP32-S2](https://www.espressif.com/en/products/socs/esp32-s2) | `v4.4` |
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| `xtensa-esp32s3-espidf` | [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) | `v4.4` |
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It is recommended to use the latest ESP-IDF stable release if possible.
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‎src/doc/rustc/src/platform-support/xtensa.md

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# `xtensa-*`
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# `xtensa-*-none-elf`
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**Tier: 3**
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The target names follow this format: `xtensa-$CPU`, where `$CPU` specifies the target chip. The following targets are currently defined:
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### `no_std`
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| Target name | Target CPU(s) |
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| ------------------------- | --------------------------------------------------------------- |
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| `xtensa-esp32-none-elf` | [ESP32](https://www.espressif.com/en/products/socs/esp32) |
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| `xtensa-esp32s2-none-elf` | [ESP32-S2](https://www.espressif.com/en/products/socs/esp32-s2) |
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| `xtensa-esp32s3-none-elf` | [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) |
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### `std`
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| Target name | Target CPU(s) |
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| ----------------------- | --------------------------------------------------------------- |
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| `xtensa-esp32-espidf` | [ESP32](https://www.espressif.com/en/products/socs/esp32) |
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| `xtensa-esp32s2-espidf` | [ESP32-S2](https://www.espressif.com/en/products/socs/esp32-s2) |
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| `xtensa-esp32s3-espidf` | [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) |
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Xtensa targets that support `std` are documented in the [ESP-IDF platform support document](esp-idf.md)
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## Building the targets
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