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Add riscv64imac_unknown_none_elf support #53308

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ingenieroariel opened this issue Aug 13, 2018 · 9 comments
Closed

Add riscv64imac_unknown_none_elf support #53308

ingenieroariel opened this issue Aug 13, 2018 · 9 comments
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A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.

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@ingenieroariel
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#52787 added support only for riscv32imac_unknown_none_elf.

I am working on riscv64imac_unknown_none_elf soft cores (running sel4) and would love to be able to use Rust, in particular: https://github.com/PolySync/cargo-fel4

I don't know the domain yet but would love to learn by going through the PR submission process to add that architecture if there are no reasons to exclude it. Are there reasons for not including riscv64imac related to hardware in the wild?

/cc @japaric

@hanna-kruppe
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RV64 support in LLVM is practically nil at this point, so we can't just generate code for it yet.

@lachlansneff
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Yeah, the riscv port of nebulet is waiting on support for riscv64 (as well as its various extensions).

@memoryruins
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I'm really excited to see interest in RV64 support in Rust and I'm keen to do what I can to support you in this. The immediate priority is pretty clear - get these patches merged upstream. Beyond that, please keep tagging me in issues that I can help with and of course file bug reports on bugs.llvm.org when appropriate.

rust-embedded/wg#218 (comment)

@tarcieri
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I'm very much interested in this as well (for use on the HiFive Unleashed)

@fintelia
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Have the relevant patches been merged at this point?

@memoryruins
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Wow, nearly all the patches have been merged to LLVM by now.
Posted an update in rust-embedded/wg#218 (comment)

@jonas-schievink jonas-schievink added A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. labels Jan 27, 2019
@nagisa nagisa added the O-riscv Target: RISC-V architecture label Jan 27, 2019
@davidlt
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davidlt commented Jan 30, 2019

I would expect to see RV64GC support within the next LLVM release. Note, that Linux distributions target RV64GC.

@Disasm
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Disasm commented Feb 17, 2019

I hope we can close the issue: riscv64imac-unknown-none-elf and riscv64gc-unknown-none-elf targets are already in nightly. Read here about some cautions: rust-embedded/wg#218 (comment)

@ingenieroariel
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Closing, thanks!

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A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
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