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adamgemmellAmanieu
adamgemmell
authored and
Amanieu
committed
Remove the bootstrap directive for cryptographic target_features
1 parent 97f5c32 commit 01c2195

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-126
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1 file changed

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‎crates/core_arch/src/arm_shared/crypto.rs

+57-126
Original file line numberDiff line numberDiff line change
@@ -51,147 +51,102 @@ extern "C" {
5151
#[cfg(test)]
5252
use stdarch_test::assert_instr;
5353

54-
// Rust compilers without 8a57820bca64a252489790a57cb5ea23db6f9198 need crypto (hence the bootstrap check)
55-
// LLVM builds without b8baa2a9132498ea286dbb0d03f005760ecc6fdb need crypto for arm (hence the target_arch check)
54+
// TODO: Use AES for ARM when the minimum LLVM version includes b8baa2a9132498ea286dbb0d03f005760ecc6fdb
5655

5756
/// AES single round encryption.
5857
#[inline]
59-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
60-
#[cfg_attr(
61-
not(any(bootstrap, target_arch = "arm")),
62-
target_feature(enable = "aes")
63-
)]
64-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
58+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "aes"))]
59+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
6560
#[cfg_attr(test, assert_instr(aese))]
6661
pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
6762
vaeseq_u8_(data, key)
6863
}
6964

7065
/// AES single round decryption.
7166
#[inline]
72-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
73-
#[cfg_attr(
74-
not(any(bootstrap, target_arch = "arm")),
75-
target_feature(enable = "aes")
76-
)]
77-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
67+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "aes"))]
68+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
7869
#[cfg_attr(test, assert_instr(aesd))]
7970
pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
8071
vaesdq_u8_(data, key)
8172
}
8273

8374
/// AES mix columns.
8475
#[inline]
85-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
86-
#[cfg_attr(
87-
not(any(bootstrap, target_arch = "arm")),
88-
target_feature(enable = "aes")
89-
)]
90-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
76+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "aes"))]
77+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
9178
#[cfg_attr(test, assert_instr(aesmc))]
9279
pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
9380
vaesmcq_u8_(data)
9481
}
9582

9683
/// AES inverse mix columns.
9784
#[inline]
98-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
99-
#[cfg_attr(
100-
not(any(bootstrap, target_arch = "arm")),
101-
target_feature(enable = "aes")
102-
)]
103-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
85+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "aes"))]
86+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
10487
#[cfg_attr(test, assert_instr(aesimc))]
10588
pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
10689
vaesimcq_u8_(data)
10790
}
10891

10992
/// SHA1 fixed rotate.
11093
#[inline]
111-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
112-
#[cfg_attr(
113-
not(any(bootstrap, target_arch = "arm")),
114-
target_feature(enable = "sha2")
115-
)]
116-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
94+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
95+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
11796
#[cfg_attr(test, assert_instr(sha1h))]
11897
pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 {
11998
vsha1h_u32_(hash_e)
12099
}
121100

122101
/// SHA1 hash update accelerator, choose.
123102
#[inline]
124-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
125-
#[cfg_attr(
126-
not(any(bootstrap, target_arch = "arm")),
127-
target_feature(enable = "sha2")
128-
)]
129-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
103+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
104+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
130105
#[cfg_attr(test, assert_instr(sha1c))]
131106
pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
132107
vsha1cq_u32_(hash_abcd, hash_e, wk)
133108
}
134109

135110
/// SHA1 hash update accelerator, majority.
136111
#[inline]
137-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
138-
#[cfg_attr(
139-
not(any(bootstrap, target_arch = "arm")),
140-
target_feature(enable = "sha2")
141-
)]
142-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
112+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
113+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
143114
#[cfg_attr(test, assert_instr(sha1m))]
144115
pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
145116
vsha1mq_u32_(hash_abcd, hash_e, wk)
146117
}
147118

148119
/// SHA1 hash update accelerator, parity.
149120
#[inline]
150-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
151-
#[cfg_attr(
152-
not(any(bootstrap, target_arch = "arm")),
153-
target_feature(enable = "sha2")
154-
)]
155-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
121+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
122+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
156123
#[cfg_attr(test, assert_instr(sha1p))]
157124
pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
158125
vsha1pq_u32_(hash_abcd, hash_e, wk)
159126
}
160127

161128
/// SHA1 schedule update accelerator, first part.
162129
#[inline]
163-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
164-
#[cfg_attr(
165-
not(any(bootstrap, target_arch = "arm")),
166-
target_feature(enable = "sha2")
167-
)]
168-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
130+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
131+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
169132
#[cfg_attr(test, assert_instr(sha1su0))]
170133
pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
171134
vsha1su0q_u32_(w0_3, w4_7, w8_11)
172135
}
173136

174137
/// SHA1 schedule update accelerator, second part.
175138
#[inline]
176-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
177-
#[cfg_attr(
178-
not(any(bootstrap, target_arch = "arm")),
179-
target_feature(enable = "sha2")
180-
)]
181-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
139+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
140+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
182141
#[cfg_attr(test, assert_instr(sha1su1))]
183142
pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
184143
vsha1su1q_u32_(tw0_3, w12_15)
185144
}
186145

187146
/// SHA256 hash update accelerator.
188147
#[inline]
189-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
190-
#[cfg_attr(
191-
not(any(bootstrap, target_arch = "arm")),
192-
target_feature(enable = "sha2")
193-
)]
194-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
148+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
149+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
195150
#[cfg_attr(test, assert_instr(sha256h))]
196151
pub unsafe fn vsha256hq_u32(
197152
hash_abcd: uint32x4_t,
@@ -203,12 +158,8 @@ pub unsafe fn vsha256hq_u32(
203158

204159
/// SHA256 hash update accelerator, upper part.
205160
#[inline]
206-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
207-
#[cfg_attr(
208-
not(any(bootstrap, target_arch = "arm")),
209-
target_feature(enable = "sha2")
210-
)]
211-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
161+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
162+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
212163
#[cfg_attr(test, assert_instr(sha256h2))]
213164
pub unsafe fn vsha256h2q_u32(
214165
hash_efgh: uint32x4_t,
@@ -220,25 +171,17 @@ pub unsafe fn vsha256h2q_u32(
220171

221172
/// SHA256 schedule update accelerator, first part.
222173
#[inline]
223-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
224-
#[cfg_attr(
225-
not(any(bootstrap, target_arch = "arm")),
226-
target_feature(enable = "sha2")
227-
)]
228-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
174+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
175+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
229176
#[cfg_attr(test, assert_instr(sha256su0))]
230177
pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
231178
vsha256su0q_u32_(w0_3, w4_7)
232179
}
233180

234181
/// SHA256 schedule update accelerator, second part.
235182
#[inline]
236-
#[cfg_attr(any(bootstrap, target_arch = "arm"), target_feature(enable = "crypto"))]
237-
#[cfg_attr(
238-
not(any(bootstrap, target_arch = "arm")),
239-
target_feature(enable = "sha2")
240-
)]
241-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
183+
#[cfg_attr(not(target_arch = "arm"), target_feature(enable = "sha2"))]
184+
#[cfg_attr(target_arch = "arm", target_feature(enable = "crypto,v8"))]
242185
#[cfg_attr(test, assert_instr(sha256su1))]
243186
pub unsafe fn vsha256su1q_u32(
244187
tw0_3: uint32x4_t,
@@ -255,11 +198,8 @@ mod tests {
255198
use std::mem;
256199
use stdarch_test::simd_test;
257200

258-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
259-
#[cfg_attr(
260-
all(not(bootstrap), target_arch = "aarch64"),
261-
simd_test(enable = "aes")
262-
)]
201+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
202+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "aes"))]
263203
unsafe fn test_vaeseq_u8() {
264204
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
265205
let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
@@ -272,11 +212,8 @@ mod tests {
272212
);
273213
}
274214

275-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
276-
#[cfg_attr(
277-
all(not(bootstrap), target_arch = "aarch64"),
278-
simd_test(enable = "aes")
279-
)]
215+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
216+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "aes"))]
280217
unsafe fn test_vaesdq_u8() {
281218
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
282219
let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
@@ -287,11 +224,8 @@ mod tests {
287224
);
288225
}
289226

290-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
291-
#[cfg_attr(
292-
all(not(bootstrap), target_arch = "aarch64"),
293-
simd_test(enable = "aes")
294-
)]
227+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
228+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "aes"))]
295229
unsafe fn test_vaesmcq_u8() {
296230
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
297231
let r: u8x16 = mem::transmute(vaesmcq_u8(data));
@@ -301,11 +235,8 @@ mod tests {
301235
);
302236
}
303237

304-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
305-
#[cfg_attr(
306-
all(not(bootstrap), target_arch = "aarch64"),
307-
simd_test(enable = "aes")
308-
)]
238+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
239+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "aes"))]
309240
unsafe fn test_vaesimcq_u8() {
310241
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
311242
let r: u8x16 = mem::transmute(vaesimcq_u8(data));
@@ -315,15 +246,15 @@ mod tests {
315246
);
316247
}
317248

318-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
319-
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
249+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
250+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
320251
unsafe fn test_vsha1h_u32() {
321252
assert_eq!(vsha1h_u32(0x1234), 0x048d);
322253
assert_eq!(vsha1h_u32(0x5678), 0x159e);
323254
}
324255

325-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
326-
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
256+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
257+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
327258
unsafe fn test_vsha1su0q_u32() {
328259
let r: u32x4 = mem::transmute(vsha1su0q_u32(
329260
mem::transmute(u32x4::new(0x1234_u32, 0x5678_u32, 0x9abc_u32, 0xdef0_u32)),
@@ -333,8 +264,8 @@ mod tests {
333264
assert_eq!(r, u32x4::new(0x9abc, 0xdef0, 0x1234, 0x5678));
334265
}
335266

336-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
337-
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
267+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
268+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
338269
unsafe fn test_vsha1su1q_u32() {
339270
let r: u32x4 = mem::transmute(vsha1su1q_u32(
340271
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -346,8 +277,8 @@ mod tests {
346277
);
347278
}
348279

349-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
350-
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
280+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
281+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
351282
unsafe fn test_vsha1cq_u32() {
352283
let r: u32x4 = mem::transmute(vsha1cq_u32(
353284
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -360,8 +291,8 @@ mod tests {
360291
);
361292
}
362293

363-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
364-
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
294+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
295+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
365296
unsafe fn test_vsha1pq_u32() {
366297
let r: u32x4 = mem::transmute(vsha1pq_u32(
367298
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -374,8 +305,8 @@ mod tests {
374305
);
375306
}
376307

377-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
378-
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
308+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
309+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
379310
unsafe fn test_vsha1mq_u32() {
380311
let r: u32x4 = mem::transmute(vsha1mq_u32(
381312
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -388,8 +319,8 @@ mod tests {
388319
);
389320
}
390321

391-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
392-
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
322+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
323+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
393324
unsafe fn test_vsha256hq_u32() {
394325
let r: u32x4 = mem::transmute(vsha256hq_u32(
395326
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -402,8 +333,8 @@ mod tests {
402333
);
403334
}
404335

405-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
406-
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
336+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
337+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
407338
unsafe fn test_vsha256h2q_u32() {
408339
let r: u32x4 = mem::transmute(vsha256h2q_u32(
409340
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -416,8 +347,8 @@ mod tests {
416347
);
417348
}
418349

419-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
420-
#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
350+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
351+
#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
421352
unsafe fn test_vsha256su0q_u32() {
422353
let r: u32x4 = mem::transmute(vsha256su0q_u32(
423354
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
@@ -429,8 +360,8 @@ mod tests {
429360
);
430361
}
431362

432-
#[cfg_attr(any(bootstrap, target_arch = "arm"), simd_test(enable = "crypto"))]
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#[cfg_attr(not(any(bootstrap, target_arch = "arm")), simd_test(enable = "sha2"))]
363+
#[cfg_attr(target_arch = "arm", simd_test(enable = "crypto"))]
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#[cfg_attr(not(target_arch = "arm"), simd_test(enable = "sha2"))]
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unsafe fn test_vsha256su1q_u32() {
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let r: u32x4 = mem::transmute(vsha256su1q_u32(
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mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),

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